Datasheet

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Low Power, 16-Bit

Buffered Sigma-Delta ADC

Data Sheet

AD7790

Rev. A Document Feedback

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FEATURES

Power

Supply: 2.5 V to 5.25 V operation

Normal: 75 μA maximum

Power-down: 1 μA maximum

RMS noise: 1.1 μV at 9.5 Hz update rate

16-bit p-p resolution

Integral nonlinearity: 3.5 ppm typical

Simultaneous 50 Hz and 60 Hz rejection

Internal clock oscillator

Programmable gain amplifier

Rail-to-rail input buffer

monitor channel

Temperature range: –40°C to +105°C

10-lead MSOP

INTERFACE

3-wire serial

SPI®, QSPI™, MICROWIRE™, and DSP compatible

Schmitt trigger on SCLK

APPLICATIONS

Smart transmitters

Battery applications

Portable instrumentation

Sensor measurement

Temperature measurement

Pressure measurement

Weigh scales

4 to 20 mA loops

FUNCTIONAL BLOCK DIAGRAM

03538-0-001

SERIAL

INTERFACE

INTERNAL

CLOCK

16-BIT

ADC

GND REFIN

AD7790

DIGITAL

PGA

BUF

GND

Figure 1.

GENERAL DESCRIPTION

The AD7790 is a low power, complete analog front end for

low frequency measurement applications. It contains a low

noise 16-bit ∑-Δ ADC with one differential input that can be

buffered or unbuffered along with a digital PGA, which allows

gains of 1, 2, 4, and 8.

The device operates from an internal clock. Therefore, the user

does not have to supply a clock source to the device. The output

data rate from the part is software programmable and can be

varied from 9.5 Hz to 120 Hz, with the rms noise equal to

1.1 μV at the lower update rate. The internal clock frequency

can be divided by a factor of 2, 4, or 8, which leads to a reduc-

tion in the current consumption. The update rate, cutoff

frequency, and settling time will scale with the clock frequency.

The part operates with a power supply from 2.5 V to 5.25 V.

When operating from a 3 V supply, the power dissipation for

the part is 225 μW maximum. It is housed in a 10-lead MSOP.

Summary of content (20 pages)

PAGE 1
Low Power, 16-Bit Buffered Sigma-Delta ADC AD7790 Data Sheet FUNCTIONAL BLOCK DIAGRAM FEATURES Power Supply: 2.5 V to 5.25 V operation Normal: 75 μA maximum Power-down: 1 μA maximum RMS noise: 1.1 μV at 9.5 Hz update rate 16-bit p-p resolution Integral nonlinearity: 3.
PAGE 2
AD7790 Data Sheet TABLE OF CONTENTS AD7790—Specifications .................................................................. 3 Reduced Current Modes ........................................................... 13 Timing Characteristics, ................................................................... 5 Digital Interface .......................................................................... 14 Absolute Maximum Ratings............................................................
PAGE 3
Data Sheet AD7790 AD7790—SPECIFICATIONS 1 Table 1. (VDD = 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(–) = GND; CDIV1 = CDIV0 = 0; GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.) Parameter ADC CHANNEL SPECIFICATION Output Update Rate ADC CHANNEL No Missing Codes 2 Resolution Output Noise Integral Nonlinearity Offset Error Offset Error Drift vs. Temperature Full-Scale Error 3 Gain Drift vs.
PAGE 4
AD7790 Data Sheet SPECIFICATIONS (continued)1 Parameter REFERENCE INPUT (continued) Normal Mode Rejection2 @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz Common Mode Rejection @ DC @ 50 Hz, 60 Hz LOGIC INPUTS All Inputs Except SCLK2 VINL, Input Low Voltage VINH, Input High Voltage SCLK Only (Schmitt-Triggered Input)2 VT(+) VT(–) VT(+) – VT(–) VT(+) VT(–) VT(+) - VT(–) Input Currents Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage2 VOL, Output Low Voltage2 VOH, Output High Voltage2 VOL, Output Low Voltage2 Floati
PAGE 5
Data Sheet AD7790 TIMING CHARACTERISTICS 1, 2 Table 2. (VDD = 2.5 V to 5.25 V; GND = 0 V, REFIN(+) = 2.5 V, REFIN(–) = GND, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V, Input Logic 1 = VDD, unless otherwise noted.
PAGE 6
AD7790 Data Sheet ISINK (1.6mA WITH VDD = 5V, 100µA WITH VDD = 3V) TO OUTPUT PIN 1.6V 50pF ISOURCE (200µA WITH VDD = 5V, 100µA WITH VDD = 3V) 03538-0-002 Figure 2. Load Circuit for Timing Characterization CS (I) t6 t1 t5 MSB DOUT/RDY (O) LSB t7 t2 t3 SCLK (I) t4 03538-0-003 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t11 t8 SCLK (I) t9 t10 DIN (I) MSB LSB 03538-0-004 I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev.
PAGE 7
Data Sheet AD7790 ABSOLUTE MAXIMUM RATINGS Table 3. (TA= 25°C, unless otherwise noted.) Parameter VDD to GND Analog Input Voltage to GND Reference Input Voltage to GND Total AIN/REFIN Current (Indefinite) Digital Input Voltage to GND Digital Output Voltage to GND Operating Temperature Range Storage Temperature Range Maximum Junction Temperature MSOP θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature Rating –0.3 V to +7 V –0.3 V to VDD + 0.3 V –0.
PAGE 8
AD7790 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 CS 2 AD7790 10 DIN 9 DOUT/RDY 8 VDD TOP VIEW AIN(–) 4 (Not to Scale) 7 GND AIN(+) 3 REF(+) 5 6 Pin No. 6 Mnemonic REFIN(–) 7 8 9 GND VDD DOUT/RDY 10 DIN REF(–) 03538-0-005 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic SCLK 2 CS 3 AIN(+) 4 AIN(–) 5 REFIN(+) Function Serial Clock Input for Data Transfers to and from the ADC.
PAGE 9
Data Sheet AD7790 TYPICAL PERFORMANCE CHARACTERISTICS 0 3.0 VDD = 5V UPDATE RATE = 16.6Hz TA = 25°C –10 –20 2.5 –30 RMS NOISE (µV) –40 dB –50 –60 –70 –80 2.0 1.5 1.0 –90 0.5 –100 –110 –120 0 0 20 40 60 80 100 FREQUENCY (Hz) 120 140 160 0 03538-0-007 Figure 6. Frequency Response for a 16.6 Hz Update Rate 0.5 1.0 1.5 2.0 2.5 3.0 VREF (V) 3.5 4.0 Figure 7. RMS Noise vs. Reference Voltage Rev. A | Page 9 of 20 4.5 5.
PAGE 10
AD7790 Data Sheet ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated. COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0) The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register.
PAGE 11
Data Sheet AD7790 STATUS REGISTER (RS1, RS0 = 0, 0; POWER-ON/RESET = 0x88) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load bits RS1 and RS0 with 0. Table 8 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream.
PAGE 12
AD7790 Data Sheet Bit Location MR2 MR1 Bit Name 0 BUF MR0 0 Description This bit must be programmed with a Logic 0 for correct operation. Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in unbuffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered mode, allowing the user to place source impedances on the front end without contributing gain errors to the system.
PAGE 13
Data Sheet AD7790 ADC CIRCUIT INFORMATION OVERVIEW The AD7790 is a low power ADC that incorporates a ∑-∆ modulator, a buffer, a PGA, and on-chip digital filtering intend-ed for the measurement of wide dynamic range, low frequency signals such as those in pressure transducers, weigh scales, and temperature measurement applications. The part has one differential input that can be buffered or unbuffered.
PAGE 14
AD7790 Data Sheet DIGITAL INTERFACE As previously outlined, the AD7790’s programmable functions are controlled using a set of on-chip registers. Data is written to these registers via the part’s serial interface and read access to the on-chip registers is also provided by this interface. All communications with the part must start with a write to the communications register. After power-on or reset, the device expects a write to its communications register.
PAGE 15
Data Sheet AD7790 Single Conversion Mode Continuous Conversion Mode In single conversion mode, the AD7790 is placed in shutdown mode between conversions. When a single conversion is initiated by setting MD1 to 1 and MD0 to 0 in the mode register, the AD7790 powers up, performs a single conversion, and then returns to shutdown mode. A conversion will require a time period of 2 × tADC. DOUT/RDY goes low to indicate the completion of a conversion.
PAGE 16
AD7790 Data Sheet Continuous Read Mode before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion or if insufficient serial clocks are applied to the AD7790 to read the word, the serial output register is reset when the next conversion is complete and the new conversion is placed in the output serial register.
PAGE 17
Data Sheet AD7790 CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL BIPOLAR CONFIGURATION The AD7790 has one differential analog input channel. This is connected to the on-chip buffer amplifier when the device is operated in buffered mode and directly to the modulator when the device is operated in unbuffered mode. In buffered mode (the BUF bit in the mode register is set to 1), the input channel feeds into a high impedance input stage of the buffer amplifier.
PAGE 18
AD7790 Data Sheet REFIN(+) without introducing gain errors in the system. Deriving the reference input voltage across an external resistor will mean that the reference input sees a significant external source impedance. External decoupling on the REFIN pins would not be recommended in this type of circuit configuration. VDD MONITOR Along with converting external voltages, the analog input channel can be used to monitor the voltage on the VDD pin.
PAGE 19
Data Sheet AD7790 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 6° 0° 0.23 0.13 0.70 0.55 0.40 COMPLIANT TO JEDEC STANDARDS MO-187-BA 091709-A 0.15 0.05 COPLANARITY 0.10 Figure 11.