Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External MSOP 10

Low Power, 16-/24-Bit,

Sigma-Delta ADCs

AD7788/AD7789

Rev. B

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FEATURES

AD7788: 16-bit resolution

AD7789: 24-bit resolution

Power

Supply: 2.5 V to 5.25 V operation

Normal: 75 μA maximum

Power-down: 1 μA maximum

RMS noise: 1.5 μV

AD7788: 16-bit p-p resolution

AD7789: 19-bit p-p resolution (21.5 bits effective)

Integral nonlinearity: 3.5 ppm typical

Simultaneous 50 Hz and 60 Hz rejection

Internal clock oscillator

monitor channel

10-lead MSOP

INTERFACE

3-wire serial

SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible

Schmitt trigger on SCLK

APPLICATIONS

Smart transmitters

Battery applications

Portable instrumentation

Sensor measurement

Temperature measurement

Pressure measurement

Weigh scales

4 to 20 mA loops

FUNCTIONAL BLOCK DIAGRAM

03539-001

SERIAL

INTERFACE

AND

CONTROL

LOGIC

CLOCK

*AD7788: 16-BIT ADC

AD7789: 24-BIT ADC

IN(+)

AIN(–)

GND

Σ-Δ

ADC*

AD7788/

AD7789

REFIN(+) REFIN(–)

DOUT/RDY

DIN

SCLK

Figure 1.

GENERAL DESCRIPTION

The AD7788/AD7789 are low power, low noise, analog front

ends for low frequency measurement applications. The AD7789

contains a low noise, 24-bit, ∑-∆ ADC with one differential

input. The AD7788 is a 16-bit version of the AD7789.

The devices operate from an internal clock. Therefore, the

user does not have to supply a clock source to the devices.

The output data rate is 16.6 Hz, which gives simultaneous

50 Hz/60 Hz rejection.

The parts operate with a single power supply from 2.5 V to

5.25 V. When operating from a 3 V supply, the power dissi-

pation for the part is 225 µW maximum. The AD7788/AD7789

are available in a 10-lead MSOP.

Summary of content (20 pages)

PAGE 1
Low Power, 16-/24-Bit, Sigma-Delta ADCs AD7788/AD7789 AD7788: 16-bit resolution AD7789: 24-bit resolution Power Supply: 2.5 V to 5.25 V operation Normal: 75 μA maximum Power-down: 1 μA maximum RMS noise: 1.5 μV AD7788: 16-bit p-p resolution AD7789: 19-bit p-p resolution (21.5 bits effective) Integral nonlinearity: 3.
PAGE 2
AD7788/AD7789 TABLE OF CONTENTS Features .............................................................................................. 1 Communications Register......................................................... 11 Interface ............................................................................................. 1 Status Register............................................................................. 12 Applications........................................................................
PAGE 3
AD7788/AD7789 SPECIFICATIONS AD7789 VDD = 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(−) = GND; GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter 1 ADC CHANNEL SPECIFICATION Output Update Rate ADC CHANNEL No Missing Codes 2 Resolution Output Noise Integral Nonlinearity Offset Error Offset Error Drift vs. Temperature Full-Scale Error 3 Gain Drift vs.
PAGE 4
AD7788/AD7789 AD7788 VDD = 2.5 V to 5.25 V (B grade); VDD = 2.7 V to 5.25 V (A grade); REFIN(+) = 2.5 V; REFIN(−) = GND; GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 ADC CHANNEL SPECIFICATION Output Update Rate ADC CHANNEL No Missing Codes 2 Resolution Output Noise Integral Nonlinearity Offset Error Offset Error Drift vs. Temperature Full-Scale Error 3 Gain Drift vs.
PAGE 5
AD7788/AD7789 AD7788/AD7789 Table 3.
PAGE 6
AD7788/AD7789 TIMING CHARACTERISTICS VDD = 2.5 V to 5.25 V (AD7788B and AD7789); VDD = 2.7 V to 5.25 V (AD7788A); GND = 0 V; REFIN(+) = 2.5 V; REFIN(−) = GND; Input Logic 0 = 0 V; Input Logic 1 = VDD, unless otherwise noted. Table 4.
PAGE 7
AD7788/AD7789 TIMING DIAGRAMS ISINK (1.6mA WITH VDD = 5V, 100µA WITH VDD = 3V) TO OUTPUT PIN 1.6V ISOURCE (200µA WITH VDD = 5V, 100µA WITH VDD = 3V) 03539-002 50pF Figure 2. Load Circuit for Timing Characterization CS (I) t6 t1 t5 MSB DOUT/RDY (O) LSB t7 t2 t3 03539-003 SCLK (I) t4 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t11 t8 SCLK (I) t9 t10 MSB LSB I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev.
PAGE 8
AD7788/AD7789 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to GND Analog Input Voltage to GND Reference Input Voltage to GND Total AIN/REFIN Current (Indefinite) Digital Input Voltage to GND Digital Output Voltage to GND Operating Temperature Range B Grade A Grade Storage Temperature Range Maximum Junction Temperature 10-Lead MSOP θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature Rating −0.3 V to +7 V −0.
PAGE 9
AD7788/AD7789 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 CS 2 AD7788/ AD7789 10 DIN 9 DOUT/RDY 8 VDD TOP VIEW AIN(–) 4 (Not to Scale) 7 GND REFIN(+) 5 6 REFIN(–) 03539-005 AIN(+) 3 Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 Mnemonic SCLK 2 CS 3 4 5 AIN(+) AIN(−) REFIN(+) 6 7 8 9 REFIN(−) GND VDD DOUT/RDY 10 DIN Description Serial Clock Input for Data Transfers to and from the ADC.
PAGE 10
AD7788/AD7789 TYPICAL PERFORMANCE CHARACTERISTICS 8388625 0 –10 –20 –30 –40 CODE dB –50 –60 –70 –80 –90 –110 –120 0 20 40 60 80 100 FREQUENCY (Hz) 120 140 160 8388591 VDD = 3V, VREF = 2.048V, TA = 25°C, RMS NOISE = 1.25µV 0 200 Figure 6. Frequency Response with 16.6 Hz Update Rate 70 400 600 READ NO. 800 1000 Figure 8. AD7789 Noise Plot 3.0 VDD = 3V VREF = 2.048V TA = 25°C RMS NOISE = 1.25µV VDD = 5V UPDATE RATE = 16.6Hz TA = 25°C 2.5 RMS NOISE (µV) 50 40 30 2.0 1.5 1.
PAGE 11
AD7788/AD7789 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated. For read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register.
PAGE 12
AD7788/AD7789 Table 8. Register Selection RS1 0 0 0 1 1 RS0 0 0 1 0 1 Register Communications register during a write operation Status register during a read operation Mode register Reserved Data register Register Size 8-bit 8-bit 8-bit 8-bit 16-bit (AD7788) 24-bit (AD7789) Table 9.
PAGE 13
AD7788/AD7789 MODE REGISTER (RS1, RS0 = 0, 1; Power-On/Reset = 0x02) The mode register is an 8-bit register from which data can be read from or written to. This register is used to configure the ADC for range, to set unipolar or bipolar mode, to enable or disable the buffer, or to place the device into power-down mode. Table 11 outlines the bit designations for the mode register. MR0 through MR7 indicate the bit locations, MR denoting the bits are in the mode register.
PAGE 14
AD7788/AD7789 ADC CIRCUIT INFORMATION The AD7788/AD7789 are low power ADCs that incorporate a Σ-Δ modulator and on-chip digital filtering intended for the measurement of wide dynamic range, low frequency signals, such as those in pressure transducers, weigh scales, and temperature measurement applications. The part has one unbuffered differential input. The device requires an external reference voltage between 0.1 V and VDD. Figure 10 shows the basic connections required to operate the part. POWER SUPPLY 0.
PAGE 15
AD7788/AD7789 The serial interface can be reset by writing a series of 1s on the DIN input. If a Logic 1 is written to the AD7788/AD7789 for at least 32 serial clock cycles, the serial interface is reset. This ensures that the interface can be reset to a known state if the interface gets lost due to a software error or a glitch in the system. Reset returns the interface to the state in which it is expecting a write to the communications register.
PAGE 16
AD7788/AD7789 Continuous Read Mode If the data-word has not read the conversion before the completion of the next conversion, or if insufficient serial clocks are applied to the AD7788/AD7789 to read the word, the serial output register is reset when the next conversion is complete and the new conversion is placed in the output serial register. Rather than write to the communications register each time a conversion is complete to access the data, the AD7788/AD7789 can be placed in continuous read mode.
PAGE 17
AD7788/AD7789 CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL DATA OUTPUT CODING The AD7788/AD7789 have one differential analog input channel that is connected to the modulator, thus, the input is unbuffered. Note that this unbuffered input path provides a dynamic load to the driving source. Therefore, resistor/capacitor combinations on the input pins can cause dc gain errors, depending on the output impedance of the source that is driving the ADC input.
PAGE 18
AD7788/AD7789 Reference voltage sources like those recommended in the previous section (for example, ADR391) typically have low output impedances and are, therefore, tolerant to having decoupling capacitors on REFIN(+) without introducing gain errors in the system. Deriving the reference input voltage across an external resistor means that the reference input sees a significant external source impedance. External decoupling on the REFIN pins is not recommended in this type of circuit configuration.
PAGE 19
AD7788/AD7789 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 6 5 5.15 4.90 4.65 PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.05 1.10 MAX 0.33 0.17 SEATING PLANE 0.23 0.08 8° 0° 0.80 0.60 0.40 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 14.