Datasheet

AD7787 Data Sheet
Rev. A | Page 4 of 20
Parameter AD7787B Unit Test Conditions/Comments
LOGIC INPUTS
All Inputs Except SCLK
1
V
INL
, Input Low Voltage 0.8 V max V
DD
= 5 V.
0.4 V max V
DD
= 3 V.
V
INH
, Input High Voltage
2.0
V min
V
DD
= 3 V or 5 V.
SCLK Only (Schmitt-Triggered Input)
1
V
T
(+) 1.4/2 V min/V max V
DD
= 5 V.
V
T
(−) 0.8/1.4 V min/V max V
DD
= 5 V.
V
T
(+) − V
T
(−) 0.3/0.85 V min/V max V
DD
= 5 V.
V
T
(+) 0.9/2 V min/V max V
DD
= 3 V.
V
T
(−)
0.4/1.1
V min/V max
V
DD
= 3 V.
V
T
(+) − V
T
(−) 0.3/0.85 V min/V max V
DD
= 3 V.
Input Currents ±1 µA max V
IN
= V
DD
or GND.
Input Capacitance 10 pF typ All Digital Inputs.
LOGIC OUTPUTS
V
OH
, Output High Voltage
1
V
DD
− 0.6 V min V
DD
= 3 V, I
SOURCE
= 100 µA.
V
OL
, Output Low Voltage
1
0.4 V max V
DD
= 3 V, I
SINK
= 100 µA.
V
OH
, Output High Voltage
1
4 V min V
DD
= 5 V, I
SOURCE
= 200 µA.
V
OL
, Output Low Voltage
1
0.4
V max
V
DD
= 5 V, I
SINK
= 1.6 mA.
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance 10 pF typ
Data Output Coding Offset Binary
POWER REQUIREMENTS
5
Power Supply Voltage
V
DD
− GND 2.5/5.25 V min/max
Power Supply Currents
I
DD
Current
6
75 µA max 65 µA typ, V
DD
= 3.6 V, unbuffered mode.
145
µA max
130 µA typ, V
DD
= 3.6 V, buffered mode.
80 µA max 73 µA typ, V
DD
= 5.25 V, unbuffered mode.
160 µA max 145 µA typ, V
DD
= 5.25 V, buffered mode.
I
DD
(Power-Down Mode) 1 µA max
1
Specification is not production tested but is supported by characterization data at initial product release.
2
Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (V
DD
= 4 V).
3
The AD7787 can tolerate absolute analog input voltages down to GND − 200 mV but the leakage current will increase.
4
FS[2:0] are the three bits used in the filter register to select the output word rate.
5
Digital inputs equal to V
DD
or GND.
6
The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 14).