Datasheet

AD7785
Rev. 0 | Page 15 of 32
STATUS REGISTER
RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x88
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,
select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0.
Tabl e 11 outlines the bit designations for the status
register. SR0 through SR7 indicate the bit locations, and SR denotes that the bits are in the status register. SR7 denotes the first bit of the
data stream. The number in parentheses indicates the power-on/reset default status of that bit.
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
RDY(1)
ERR(0) 0(0) 0(0) 1 (1) CH2(0) CH1(0) CH0(0)
Table 11. Status Register Bit Designations
Bit Location Bit Name Description
SR7
RDY Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically
after the ADC data register has been read or a period before the data register is updated with a new
conversion result to indicate to the user not to read the conversion data. It is also set when the part is
placed in power-down mode. The end of a conversion is indicated by the DOUT/
RDY pin also. This pin can
be used as an alternative to the status register for monitoring the ADC for conversion data.
SR6 ERR
ADC Error Bit. This bit is written to at the same time as the
RDY bit. Set to indicate that the result written to
the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange and underrange.
Cleared by a write operation to start a conversion.
SR5 to SR4 0 These bits are automatically cleared.
SR3 1 This bit is automatically set on the AD7785.
SR2 to SR0 CH2 to CH0 These bits indicate which channel is being converted by the ADC.
MODE REGISTER
RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A
The mode register is a 16-bit register from which data can be read or to which data can be written. This register is used to select the
operating mode, update rate, and clock source.
Tabl e 12 outlines the bit designations for the mode register. MR0 through MR15 indicate
the bit locations, MR denoting the bits are in the mode register. MR15 denotes the first bit of the data stream. The number in parentheses
indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter and sets the
RDY
bit.
MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8
MD2(0) MD1(0) MD0(0) 0(0) 0(0) 0(0) 0(0) 0(0)
MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0
CLK1(0) CLK0(0) 0(0) 0(0) FS3(1) FS2(0) FS1(1) FS0(0)
Table 12. Mode Register Bit Designations
Bit Location Bit Name Description
MR15 to MR13 MD2 to MD0 Mode Select Bits. These bits select the operational mode of the AD7785 (see Table 13).
MR12 to MR8 0 These bits must be programmed with a Logic 0 for correct operation.
MR7 to MR6 CLK1 to CLK0
These bits are used to select the clock source for the AD7785. Either an on-chip 64 kHz clock or an external
clock can be used. The ability to override using an external clock allows several AD7785 devices to be
synchronized. In addition, 50 Hz/60 Hz is improved when an accurate external clock drives the AD7785.
CLK1 CLK0 ADC Clock Source
0 0 Internal 64 kHz Clock. Internal clock is not available at the CLK pin.
0 1 Internal 64 kHz Clock. This clock is made available at the CLK pin.
1 0
External 64 kHz Clock Used. An external clock gives better 50 Hz/60 Hz rejection. See
specifications for external clock.
1 1 External Clock Used. The external clock is divided by 2 within the AD7785.
MR5 to MR4 0 These bits must be programmed with a Logic 0 for correct operation.
MR3 to MR0 FS3 to FS0 Filter Update Rate Select Bits (see Table 14).