Datasheet

–4–
TIMING CHARACTERISTICS
1, 2
(V
DD
= 2.7 V to 3.6 V or V
DD
= 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V,
Logic 1 = V
DD
unless otherwise noted.)
Limit at T
MIN
, T
MAX
Parameter (B Version) Unit Conditions/Comments
t
1
30.5176 µs typ Crystal Oscillator Period
t
ADC
50.54 ms typ 19.79 Hz Update Rate
t
2
0 ns min CH1/CH2 Select to CS Setup Time
t
3
0 ns min CS Falling Edge to DOUT Active
60 ns max V
DD
= 4.75 V to 5.25 V
80 ns max V
DD
= 2.7 V to 3.6 V
t
4
2 × t
ADC
ns typ Channel Settling Time
t
5
3
0 ns min SCLK Active Edge to Data Valid Delay
4
60 ns max V
DD
= 4.75 V to 5.25 V
80 ns max V
DD
= 2.7 V to 3.6 V
t
8
5
10 ns min Bus Relinquish Time after CS Inactive Edge
80 ns max
t
9
0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time
t
10
10 ns min SCLK Inactive to DOUT High
80 ns max
Slave Mode Timing
t
6
100 ns min SCLK High Pulsewidth
t
7
100 ns min SCLK Low Pulsewidth
Master Mode Timing
t
6
t
1
/2 µs typ SCLK High Pulsewidth
t
7
t
1
/2 µs typ SCLK Low Pulsewidth
t
11
t
1
/2 µs min DOUT Low to First SCLK Active Edge
4
3t
1
/2 µs max
NOTES
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 2.
3
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
4
SCLK active edge is falling edge of SCLK.
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part
and as such are independent of external bus loading capacitances.
TO OUTPUT
PIN
50pF
I
SINK
(1.6mA WITH V
DD
= 5V
100␮A WITH V
DD
= 3V)
1.6V
I
SOURCE
( 200␮A WITH V
DD
= 5V
100␮A WITH V
DD
= 3V)
Figure 1. Load Circuit for Timing Characterization
AD7782
REV. A