Datasheet

AD7780
Rev. A | Page 5 of 16
TIMING CHARACTERISTICS
AV
DD
= 2.7 V to 5.25 V, DV
DD
= 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DV
DD
, unless otherwise noted.
Table 3.
Parameter
1
Limit at T
MIN
, T
MAX
Unit Test Conditions/Comments
Read
2
t
1
100 ns min SCLK high pulse width
t
2
100 ns min SCLK low pulse width
t
3
3
0 ns min SCLK active edge to data valid delay
4
60 ns max DV
DD
= 4.75 V to 5.25 V
80 ns max DV
DD
= 2.7 V to 3.6 V
t
4
10 ns min
SCLK inactive edge to DOUT/RDY
high
130 ns max
Reset
t
5
100 ns min
PDRST
low pulse width
t
6
5
FILTER/GAIN change to data valid delay
120 ms typ Update rate = 16.7 Hz
300 ms typ Update rate = 10 Hz
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 3.
3
The values of t
3
are measured using the load circuit of Figure 2 and are defined as the time required for the output to cross the V
OL
or V
OH
limits.
4
SCLK active edge is falling edge of SCLK.
5
The
PDRST
high to data valid delay is typically 1 ms longer than t
6
because the internal oscillator requires time to power up and settle.
Circuit and Timing Diagrams
I
SINK
(1.6mA WITH DV
DD
= 5V,
100µA WITH DV
DD
= 3V)
I
SOURCE
(200µA WITH DV
DD
= 5V,
100µA WITH DV
DD
= 3V)
1.6V
TO
OUTPUT
PIN
50pF
07945-002
Figure 2. Load Circuit for Timing Characterization
DOUT/RDY
(OUTPUT)
MSB LSB
SCLK
(INPUT)
t
3
t
1
t
4
t
2
07945-003
Figure 3. Read Cycle Timing Diagram
PDRST
(INPUT)
t
5
DOUT/RDY
(OUTPUT)
07945-004
Figure 4. Resetting the AD7780
GAIN OR FILTER
(INPUT)
t
6
DOUT/RDY
(OUTPUT)
07945-005
Figure 5. Changing Gain or Filter Option