Datasheet

AD7767
Rev. C | Page 9 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
06859-006
1
2
3
4
5
6
7
8
V
REF+
REFGND
V
IN+
SYNC/PD
AGND
V
IN–
AV
DD
DV
DD
16
15
14
13
12
11
10
9
SDI
MCLK
SCLK
SDO
V
DRIVE
DGND
DRDY
CS
AD7767/
AD767-1/
AD7767-2
TOP VIEW
(Not to Scale)
Figure 6. 16-Lead TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 AV
DD
+2.5 V Analog Power Supply.
2 V
REF+
Reference Input for the AD7767. An external reference must be applied to this input pin. The V
REF+
input can range
from 2.4 V to 5 V. The reference voltage input is independent of the voltage magnitude applied to the AV
DD
pin.
3 REFGND
Reference Ground. Ground connection for the reference voltage. The input reference voltage (V
REF+
) should be
decoupled to this pin.
4 V
IN+
Positive Input of the Differential Analog Input.
5 V
IN−
Negative Input of the Differential Analog Input.
6 AGND Power Supply Ground for Analog Circuitry.
7
SYNC
/PD Synchronization and Power-Down Input Pin. This pin has dual functionality. It can be used to synchronize multiple
AD7767 devices and/or to put the AD7767 device into power-down mode. See the Power-Down, Reset, and
Synchronization section for further details.
8 DV
DD
2.5 V Digital Power Supply Input. In cases where an logic voltage of 2.5 V is used for interfacing (2.5 V applied to
V
DRIVE
pin), the DVDD and V
DRIVE
pin may be connected to the same voltage supply rail.
9 V
DRIVE
Logic Power Supply Input, 1.8 V to 3.6 V. The voltage supplied at this pin determines the operating voltage of the
digital logic interface.
10 SDO
Serial Data Output. The conversion result from the AD7767 is output on the SDO pin as a 24-bit, twos complement,
MSB first, serial data stream.
11 DGND Digital Logic Power Supply Ground.
12
DRDY
Data Ready Output. A falling edge on the DRDY signal indicates that a new conversion data result is available in the
output register of the AD7767. See the section for further details. AD7767 Interface
13 SCLK
Serial Clock Input. The SCLK input provides the serial clock for all serial data transfers with the AD7767 device. See
the AD7767 Interface section for further details.
14 MCLK Master Clock Input. The AD7767 sampling frequency is equal to the MCLK frequency.
15 SDI Serial Data Input. This is the daisy-chain input of the AD7767. See the Daisy Chaining section for further details.
16
CS
Chip Select Input. The CS input selects the AD7767 device and acts as an enable on the SDO pin. In cases where CS
is used, the MSB of the conversion result is clocked onto the SDO line on the CS
falling edge. The CS input allows
multiple AD7767 devices to share the same SDO line. This allows the user to select the appropriate device by
supplying it with a logic low CS
signal, which enables the SDO pin of the device concerned. See the
section for further details.
AD7767
Interface