Datasheet

AD7766
Rev. C | Page 6 of 24
TIMING DIAGRAMS
MCLK
1
DRDY
t
2
t
3
t
4
t
1
t
READ
t
5
t
5
t
DRDY
8 × n 8 × n1
06449-002
Figure 2.
DRDY
vs. MCLK Timing Diagram, n = 1 for AD7766 (Decimate by 8), n = 2 for AD7766-1 (Decimate by 16), n = 4 for AD7766-2 (Decimate by 32)
06449-003
DRDY
CS
SCLK
SDO
t
DRDY
t
READ
D22MSB D21 D20 D1 LSB
t
6
t
13
t
12
1 23
t
10
t
11
t
7
t
8
t
9
Figure 3. Serial Timing Diagram, Reading Data Using
CS
06449-004
CS = 0
SCLK
SDO
DATA
INVALID
MSB D22 D21 D20 D1 LSB
DATA
INVALID
DRDY
t
DRDY
t
READ
1 23 24
t
14
t
8
t
9
t
15
t
11
t
10
Figure 4. Serial Timing Diagram, Reading Data Setting
CS
Logic Low