Datasheet

AD7766
Rev. C | Page 5 of 24
TIMING SPECIFICATIONS
AV
DD
= DV
DD
= 2.5 V ± 5%, V
DRIVE
= 1.7 V to 3.6 V, V
REF+
= 5 V, common-mode input = V
REF+
/2, T
A
= −40°C (T
MIN
) to +105°C (T
MAX
),
unless otherwise noted.
1
Table 3.
Parameter Limit at t
MIN
, t
MAX
Unit Description
DRDY OPERATION
t
1
510 ns typ
MCLK rising edge to DRDY
falling edge
t
2
2
100 ns min MCLK high pulse width
t
3
2
900 ns max MCLK low pulse width
t
4
265 ns typ
MCLK rising edge to DRDY
rising edge (AD7766)
128 ns typ
MCLK rising edge to DRDY
rising edge (AD7766-1)
71 ns typ
MCLK rising edge to DRDY
rising edge (AD7766-2)
t
5
294 ns typ
DRDY
pulse width (AD7766)
435 ns typ
DRDY
pulse width (AD7766-1)
492 ns typ
DRDY
pulse width (AD7766-2)
t
READ
3
t
DRDY
− t
5
ns typ
DRDY
low period, read data during this period
t
DRDY
3
n × 8 × t
MCLK
ns typ
DRDY
period
READ OPERATION
t
6
0 ns min
DRDY
falling edge to CS setup time
t
7
6 ns max
CS
falling edge to SDO tristate disabled
t
8
60 ns max Data access time after SCLK falling edge (V
DRIVE
= 1.7 V)
50 ns max Data access time after SCLK falling edge (V
DRIVE
= 2.3 V)
25 ns max Data access time after SCLK falling edge (V
DRIVE
= 2.7 V)
24 ns max Data access time after SCLK falling edge (V
DRIVE
= 3.0 V)
t
9
10 ns min SCLK falling edge to data valid hold time (V
DRIVE
= 3.6 V)
t
10
10 ns min SCLK high pulse width
t
11
10 ns min SCLK low pulse width
t
SCLK
1/t
8
sec min Minimum SCLK period
t
12
6 ns max
Bus relinquish time after CS
rising edge
t
13
0 ns min
CS
rising edge to DRDY rising edge
READ OPERATION WITH CS LOW
t
14
0 ns min
DRDY
falling edge to data valid setup time
t
15
0 ns max
DRDY
rising edge to data valid hold time
DAISY-CHAIN OPERATION
t
16
1 ns min SDI valid to SCLK falling edge setup time
t
17
2 ns max SCLK falling edge to SDI valid hold time
SYNC/PD OPERATION
t
18
1 ns typ
SYNC
/PD falling edge to MCLK rising edge
t
19
20 ns typ
MCLK rising edge to DRDY
rising edge going into SYNC/PD mode
t
20
1 ns min
SYNC
/PD rising edge to MCLK rising edge
t
21
510 ns typ
MCLK rising edge to DRDY
falling edge coming out of SYNC/PD mode
t
SETTLING
3
(592 × n) + 2 t
MCLK
Filter settling time after a reset or power-down
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.7 V.
2
t
2
and t
3
allow a ~90% to 10% duty cycle to be used for the MCLK input, where the minimum is 10% for the clock high time and 90% for MCLK low time. The maximum
MCLK frequency is 1.024 MHz.
3
n = 1 for AD7766, n = 2 for the AD7766-1, n = 4 for the AD7766-2.