Datasheet

AD7765
Rev. A | Page 25 of 32
CLOCKING THE AD7765
The AD7765 requires an external low jitter clock source. This
signal is applied to the MCLK pin. An internal clock signal
(ICLK) is derived from the MCLK input signal. The ICLK
controls the internal operation of the AD7765. The maximum
ICLK frequency is
20 MHz. To generate the ICLK,
ICLK = MCLK/2
For output data rates equal to those used in audio systems, a
12.288 MHz ICLK frequency can be used. As shown in Table 6,
output data rates of 96 kHz and 48 kHz are achievable with this
ICLK frequency.
MCLK JITTER REQUIREMENTS
The MCLK jitter requirements depend on a number of factors
and are given by
20
)dB(
102
)(
SNR
f
OSR
t
IN
rmsj
××π×
=
where:
OSR = oversampling ratio = f
ICLK
/ODR.
f
IN
= maximum input frequency.
SNR (dB) = target SNR.
Example 1
This example can be taken from Table 6, where:
ODR = 156.25 kHz.
f
ICLK
= 20 MHz.
f
IN
(max) = 78.625 kHz.
SNR = 104 dB.
ps29.102
1010625.782
128
35.53
)(
=
×××π×
=
rmsj
t
This is the maximum allowable clock jitter for a full-scale,
78.625 kHz input tone with the given ICLK and output
data rate.
Example 2
This second example can also be taken from Table 6, where:
ODR = 48 kHz.
f
ICLK
= 12.288 MHz.
f
IN
(max) = 19.2 kHz.
SNR = 109 dB.
ps470
10102.192
256
45.53
)(
=
×××π×
=
rmsj
t
The input amplitude also has an effect on these jitter figures.
For example, if the input level is 3 dB below full scale, the
allowable jitter is increased by a factor of √2, increasing the first
example to 144.65 ps rms. This happens when the maximum
slew rate is decreased by a reduction in amplitude.
Figure 43 and Figure 44 illustrate this point, showing the maxi-
mum slew rate of a sine wave of the same frequency but with
different amplitudes.
1.0
–1.0
0.5
0
–0.5
06519-022
Figure 43. Maximum Slew Rate of a Sine Wave
with an Amplitude of 2 V p-p
1.0
–1.0
0.5
0
–0.5
06519-023
Figure 44. Maximum Slew Rate of the Same Frequency Sine Wave as in
Figure 43 with an Amplitude of 1 V p-p