Datasheet

AD7764
Rev. A | Page 7 of 32
TIMING DIAGRAMS
D22
D23
D21
D20
D19
D1
D0
ST4 ST3
ST2
ST1
ST0
0
0
0
SCO (O)
FSO (O)
SDO (O)
t
1
t
9
32 × t
SCO
t
2
t
8
t
3
t
4
t
5
t
7
t
6
06518-002
Figure 2. Serial Read Timing Diagram
RA15 RA14
RA13
RA12 RA11
RA10 RA9 RA8
RA1
RA0 D15
D14
D1 D0
SCO (O)
FSI (I)
SDI (I)
t
12
t
1
t
10
t
13
t
14
t
15
t
11
t
2
06518-003
Figure 3. AD7764 Register Write
STATUS REGISTER
CONTENTS [31:16]
DON’T CARE
BITS [15:0]
SCO (O)
SDO (O)
FSI (I)
SDI (I)
FSO (O)
≥8 × t
SCO
NEXT DATA READ FOLLOWING THE WRITE TO CONTROL REGISTER
CONTROL REGISTER
ADDR (0x0001)
CONTROL REGISTER
INSTRUCTION
06518-004
Figure 4. AD7764 Status Register Read Cycle