Datasheet

AD7764
Rev. A | Page 6 of 32
TIMING SPECIFICATIONS
AV
DD
1 = DV
DD
= 2.5 V, AV
DD
2 = AV
DD
3 = AV
DD
4 = 5 V, V
REF
+ = 4.096 V, T
A
= 25°C, C
LOA D
= 25 pF.
Table 3.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
MCLK
500 kHz min Applied master clock frequency
40 MHz max
f
ICLK
250 kHz min Internal modulator clock derived from MCLK
20 MHz max
t
1
1 × t
ICLK
typ SCO high period
t
2
1 × t
ICLK
typ SCO low period
t
3
1 ns typ SCO rising edge to
FSO
falling edge
t
4
2 ns typ Data access time,
FSO
falling edge to data active
t
5
8 ns max MSB data access time, SDO active to SDO valid
t
6
40 ns min Data hold time (SDO valid to SCO rising edge)
t
7
9.5 ns max Data access time (SCO rising edge to SDO valid)
t
8
2 ns typ SCO rising edge to
FSO
rising edge
t
9
32 × t
SCO
max
FSO
low period
t
10
12 ns min Setup time from
FSI
falling edge to SCO falling edge
t
11
1 × t
SCO
min
FSI
low period
t
12
1
32 × t
SCO
max
FSI
low period
t
13
12 ns min SDI setup time for the first data bit
t
14
12 ns min SDI setup time
t
15
0 ns max SDI hold time
t
R
MIN
1 × t
MCLK
min Minimum time for a valid
RESET
pulse
t
R HOLD
5 ns min Minimum time between the MCLK rising edge and
RESET
rising edge
t
R SETUP
5 ns min Minimum time between the
RESET
rising edge and MCLK rising edge
t
S
MIN
4 × t
MCLK
min Minimum time for a valid
SYNC
pulse
t
S HOLD
5 ns min Minimum time between the MCLK falling edge and
SYNC
rising edge
t
S SETUP
5 ns min Minimum time between the
SYNC
rising edge and MCLK falling edge
1
This is the maximum time FSI can be held low when writing to an individual device (a device that is not daisy-chained).