Datasheet

AD7764
Rev. A | Page 5 of 32
Parameter Test Conditions/Comments Specification Unit
REFERENCE INPUT/OUTPUT
V
REF+
Input Voltage AV
DD
3 = 5 V ± 5% 4.096 V
V
REF+
Input DC Leakage Current ±1 µA max
V
REF+
Input Capacitance 5 pF typ
DIGITAL INPUT/OUTPUT
MCLK Input Amplitude 2.25 to 5.25 V
Input Capacitance 7.3 pF typ
Input Leakage Current ±1 μA/pin max
V
INH
0.8 × DV
DD
V min
V
INL
0.2 × DV
DD
V max
V
OH
4
2.2 V min
V
OL
0.1 V max
ON-CHIP DIFFERENTIAL AMPLIFIER
Input Impedance >1
Bandwidth for 0.1 dB Flatness 125 kHz
Common-Mode Input Voltage Voltage range at input pins: V
IN
A+ and V
IN
A− 0.5 to +2.2 V
Common-Mode Output Voltage On-chip differential amplifier pins: V
OUT
A+ and V
OUT
A− 2.048 V
POWER REQUIREMENTS
AV
DD
1 (Modulator Supply) ±5% 2.5 V
AV
DD
2 (General Supply) ±5% 5 V
AV
DD
3 (Differential Amplifier Supply) ±5% 5 V min/max
AV
DD
4 (Ref Buffer Supply) ±5% 5 V min/max
DV
DD
±5% 2.5 V
Normal Power Mode
AI
DD
1 (Modulator) 19 mA typ
AI
DD
2 (General)
5
MCLK = 40 MHz 13 mA typ
AI
DD
3 (Differential Amplifier) AV
DD
3 = 5 V 10 mA typ
AI
DD
4 (Reference Buffer) AV
DD
4 = 5 V 9 mA typ
DI
DD
5
MCLK = 40 MHz 37 mA typ
Low Power Mode
AI
DD
1 (Modulator) 10 mA typ
AI
DD
2 (General)
5
MCLK = 40 MHz 7 mA typ
AI
DD
3 (Differential Amplifier) AV
DD
3 = 5 V 5.5 mA typ
AI
DD
4 (Reference Buffer) AV
DD
4 = 5 V 5 mA typ
DI
DD
5
MCLK = 40 MHz 20 mA typ
POWER DISSIPATION
Normal Power Mode MCLK = 40 MHz, decimate 64× 300 mW typ
371 mW max
Low Power Mode MCLK = 40 MHz, decimate 64× 160 mW typ
215 mW max
Power-Down Mode
6
PWRDWN
1 held logic low mW typ
1
See the Terminology section.
2
SNR specifications in decibels are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
3
Output data rate (ODR) = [(MCLK/2)]/decimation rate. That is, the maximum ODR for AD7764 = [(40 MHz)/2)/64] = 312.5 kHz.
4
Tested with a 400 µA load current.
5
Tested at MCLK = 40 MHz. This current scales linearly with the MCLK frequency applied.
6
Tested at 125°C.