Datasheet

AD7764
Rev. A | Page 23 of 32
POWER MODES
Low Power Mode
During power-up, the AD7764 defaults to operate in normal
power mode. There is no register write required.
The AD7764 also offers low power mode. To operate the device
in low power mode, the user sets the LPWR bit in the control
register to logic high (see Figure 43). Operating the AD7764 in
low power mode has no impact on the output data rate or
available bandwidth.
SCO (O)
CONTROL REGISTER
ADDRESS 0x0001
LOW POWER MODE
DATA 0x0010
FSI (I)
SDI (I)
32 × t
SCO
06518-017
Figure 43. Write Scheme for Low Power Mode
RESET/
The AD7764 features a
PWRDWN Mode
RESET
/
PWRDWN
pin. Holding the
input to this pin logic low places the AD7764 in power-down
mode. All internal circuitry is reset. Apply a
RESET
pulse to the
AD7764 after initial power-up of the device.
The AD7764
RESET
pin is polled by the rising edge of MCLK.
The AD7764 device goes into reset when an MCLK rising
senses the
RESET
input signal to be logic low. AD7764 comes
out of
RESET
on the first MCLK rising edge that senses
RESET
The best practice is to ensure that all transitions of
to be logic high.
RESET
occur synchronously with the falling edge of MCLK; otherwise,
adhere to the timing requirements shown in Figure 44.
RESET
should be kept at logic low for a minimum of one
MCLK period for a valid reset to occur.
In cases where multiple AD7764 devices are being synchronized
using the
SYNC
pulse and in the case of daisy chaining multiple
AD7764 devices, a common
RESET
pulse must be provided in
addition to the common
06518-304
MCLK
t
R MIN
1 × t
MCLK
t
R HOLD
t
R SETUP
RESET
SYNC
and MCLK signals.
Figure 44.
RESET
DECIMATION RATE PIN
Timing Synchronous to MCLK
The decimation rate of the AD7764 is selected using the
DEC_RATE pin. Table 11 shows the voltage input settings
required for each of the three decimation rates.
Table 11. DEC_RATE Pin Settings
Decimate DEC_RATE Pin Maximum Output Data Rate
64× DV
DD
312.5 kHz
128× Floating 156.25 kHz
256× GND 78.125 kHz