Datasheet

Data Sheet AD7763
Rev. B | Page 5 of 32
TIMING SPECIFICATIONS
AV
DD1
= DV
DD
= V
DRIVE
= 2.5 V, AV
DD2
= AV
DD3
= AV
DD4
= 5 V, T
A
= 25°C, normal mode, unless otherwise noted.
Table 3.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
MCLK
1 MHz min Applied master clock frequency
40 MHz max
f
ICLK
500 kHz min Internal modulator clock derived from MCLK
20 MHz max
t
1
1
1 × t
ICLK
or 0.5 × t
ICLK
2
typ SCO high period
t
2
1
1 × t
ICLK
or 0.5 × t
ICLK
2
typ SCO low period
t
3
t
SCO
3
typ
DRDY low period
t
3A
4
2 ns typ
SCO rising edge to
DRDY falling edge
t
3B
4
3 ns typ
SCO rising edge to
DRDY rising edge
t
4
5
32 × t
SCO
3
typ
FSO low period
t
4A
4, 5
1 ns typ
SCO rising edge to
FSO falling edge
t
4B
4, 5
2 ns typ
SCO falling edge to
FSO rising edge
t
5
6.5
ns max
Initial data access time
t
6
4
5 ns max SCO rising edge to SDO valid
t
7
0.5 × t
SCO
3
ns min SDO valid after SCO falling edge
t
8
16 × t
SCO
3
typ
DRDY rising edge to SDL falling edge
t
9
t
SCO
3
typ SDL pulse width
t
10
5.5 ns max SDO three-state to SCO rising edge
t
11
1 × t
SCO
3
min
FSI low period
t
12
12 ns min SDI setup time
t
13
10 ns min SDI hold time
t
14
12 ns min
FSI setup time
t
15
16 × t
SCO
3
typ SDL falling edge to SDL falling edge
1
t
ICLK
= 1/f
ICLK
.
2
SCO frequency selected by SCR and
CDIV
pins.
3
t
SCO
= t
1
+ t
2
.
4
All edges mentioned refer to SCP = 0. Invert SCO edges for SCP = 1.
5
In decimate × 32 mode, this time specification applies only when
CDIV
= 0 and SCR =1. For all other combinations of
CDIV
and SCR in decimate × 32 mode, the FSO
signal is constantly logic low.