Datasheet

AD7763 Data Sheet
Rev. B | Page 18 of 32
READING DATA USING THE I
2
S INTERFACE
The AD7763 has the capability of operating using an I
2
S
interface. The interface is functional only for the output of
stereo data and does not apply to writing to control registers,
programming coefficients for the digital filter, or the reading of
any information contained in the AD7763 onboard registers.
All of these operations must be undertaken using the normal
serial interface.
The I
2
S interface operates using two AD7763 devices. The pins
shown in Table 9 are used as the output pins for the SCK (serial
clock), SD (serial data), and WS (word select) signals for the I
2
S
interface.
Table 9.
SPI Pins I
2
S Signals
FSO
WS
SDO SD
SCO SCK
To enable the I
2
S interface, the I
2
S pin is set to logic high. The
Share Pins SH[2:0] of both AD7763 devices that use the I
2
S
interface are set to 001. The Address Pins ADR[2:0] of the two
devices must also be set to 000 and 001, respectively.
The WS and SCK signals that are used for the interface can be
taken from either AD7763 device. Note that the device that is
assigned Address 000 is defined as the left channel, and its data
is output on the SD line when WS is logic low.
The WS and SCK signals can be taken from the appropriate
pins on either of the AD7763 devices using the I
2
S interface.
The SD pins of both devices must be connected together, as
shown in Figure 27.
Data is clocked out on the SD line in accordance with Figure 28.
Because Device A is assigned Address 000, it is defined as the
left channel. The 32-bit conversion result from the left channel
is clocked out when WS is logic low, with the MSB being clocked
out first. Each 32-bit result consists of 24 data bits in twos
complement format, followed by eight status bits, as shown in
the following bit map.
D7 D6 D5 D4 D3 D2 D1 D0
DVALID OVR UFILTER LPWR FILTER_OK ADR0 0
Three-
State
AD7763
(000)
MCLK
LEFT CHANNEL
RIGHT CHANNEL
DEVICE
ADDRESS
000
DEVICE
ADDRESS
001
1
001
ADR[2:0]
FSO
WS
A
SH[2:0]
I
2
S
SH[2:0]
MCLK
SCO
SDO
SD
SCK
3-WIRE
I
2
S INTERFACE
05476-026
AD7763
(001)
MCLK
1
SH[2:0] SDO
B
ADR[2:0]
I
2
S
Figure 27. Two AD7763 Devices Operating Using the I
2
S Interface
Conversion results from Device B, assigned Address 001, are
clocked out on the SD line when WS is logic high. The SD line
goes into three-state on the falling edge of the 32nd SCK after
the falling edge of WS (left channel data) and also on the falling
edge of the 32nd SCK after the rising edge of WS (right channel
data). This permits swapping of the SD bus between the left and
right channel devices without contention.
In decimate × 32 mode the I
2
S interface is operational only
when
CDIV
= 0 and SCR = 1. The interface operates for all
combinations of SCR and
CDIV
in all other modes of
decimation.
The
DRDY
pulse still operates as in the normal serial SPI-type
interface, pulsing low immediately prior to the falling edge of
WS but having no meaning in the I
2
S interface specification.
ST1ST2D21
THREE-
STATE
D22
THREE-
STATE
THREE-
STATE
D23D21D22
RIGHT CHANNEL
DEVICE B
(WORD n – 1)
RIGHT CHANNEL
DEVICE B
(WORD n + 1)
LEFT CHANNEL
DEVICE A
(WORD n + 2)
LEFT CHANNEL
DEVICE A
(WORD n)
D23
SCK A (O)
WS A (O)
SD (O)
ST1ST2
05476-027
Figure 28. Timing Diagram for I
2
S Interface