Datasheet

Data Sheet AD7762
Rev. A | Page 5 of 28
TIMING SPECIFICATIONS
AV
DD1
= DV
DD
= V
DRIVE
= 2.5 V, AV
DD2
= AV
DD3
= AV
DD4
= 5 V, T
A
= 25°C, normal mode, unless otherwise noted.
Tabl e 3.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
MCLK
1 MHz min Applied master clock frequency
40 MHz max
f
ICLK
500 kHz min Internal modulator clock derived from MCLK
20 MHz max
t
1
1, 2
0.5 × t
ICLK
typ
DRDY pulse width
t
2
10 ns min
DRDY falling edge to CS falling edge
t
3
3 ns min
RD/WR setup time to CS falling edge
t
4
(0.5 × t
ICLK
) + 16 ns max Data access time
t
5
t
ICLK
min
CS low read pulse width
t
6
t
ICLK
min
CS high pulse width between reads
t
7
3 ns min
RD/WR hold time to CS rising edge
t
8
11 ns max Bus relinquish time
t
9
4 × t
ICLK
min
CS low write pulse width
t
10
4 × t
ICLK
min
CS high period between address and data
t
11
5 ns min Data setup time
t
12
0 ns min Data hold time
1
t
ICLK
= 1/f
ICLK
.
2
When ICLK = MCLK,
DRDY
pulse width depends on the mark/space ratio of applied MCLK.
TIMING DIAGRAMS
DATA MSW LSW + STATUS
05477-002
t
5
t
8
t
7
t
6
t
3
t
4
t
2
t
1
D[0:15]
CS
RD/WR
DRDY
Figure 2. Parallel Interface Timing Diagram
t
9
D[0:15]
CS
RD/WR
t
10
t
11
t
12
REGISTER ADDRESS REGISTER DATA
05477-004
Figure 3. AD7762 Register Write