AD7760
Rev. A | Page 7 of 36
TIMING DIAGRAMS
DATA MSW LSW + STATUS
t
5
t
8
t
7
t
6
t
3
t
4
t
2
t
1
D[0:15]
CS
RD/WR
DRDY
04975-002
Figure 2. Filtered Output—Parallel Interface Timing Diagram
t
15
D[0:15]
CS
RD/WR
t
16
t
17
t
18
REGISTER ADDRESS REGISTER DATA
04975-004
Figure 3. AD7760 Register Write
