Datasheet

AD7760
Rev. A | Page 6 of 36
TIMING SPECIFICATIONS
AV
DD
1 = DV
DD
= V
DRIVE
= 2.5 V, AV
DD
2 = AV
DD
3 = AV
DD
4 = 5 V, T
A
= 25°C, normal mode, unless otherwise noted.
Table 3.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
MCLK
1 MHz min Applied master clock frequency
40 MHz max
f
ICLK
500 kHz min Internal modulator clock derived from MCLK
20 MHz max
t
1
1, 2
0.5 × t
ICLK
typ
DRDY pulse width
t
2
10 ns min
DRDY falling edge to CS falling edge
t
3
3 ns min
RD/WR setup time to CS falling edge
t
4
(0.5 × t
ICLK
) + 16 ns max Data access time
t
5
t
ICLK
min
CS low read pulse width
t
6
t
ICLK
min
CS high pulse width between reads
t
7
3 ns min
RD/WR hold time to CS rising edge
t
8
11 ns max Bus relinquish time
t
9
2
0.5 × t
ICLK
typ
DRDY high period
t
10
2
0.5 × t
ICLK
typ
DRDY low period
t
11
(0.5 × t
ICLK
) + 16 ns max Data access time
t
12
3, 4
23 ns min
Data valid prior to
DRDY rising edge
t
13
3, 4
19 ns min
Data valid after
DRDY rising edge
t
14
11 ns max Bus relinquish time
t
15
4 × t
ICLK
min
CS low write pulse width
t
16
4 × t
ICLK
min
CS high period between address and data
t
17
5 ns min Data setup time
t
18
0 ns min Data hold time
t
19
4, 5
23 ns min
Data valid prior to MCLK falling edge while
DRDY is logic low
t
20
4, 5
19 ns min
Data valid after MCLK falling edge while
DRDY is logic low
1
t
ICLK
= 1/f
ICLK
.
2
When ICLK = MCLK,
DRDY
pulse width depends on the mark-space ratio of applied MCLK.
3
Valid when using the modulator output mode with
CDIV
= 1.
4
See the Modulator Data Output Mode section for timing diagrams.
5
Valid when using the modulator output mode with
CDIV
= 0.