Datasheet

AD7760
Rev. A | Page 28 of 36
DECOUPLING AND LAYOUT RECOMMENDATIONS
Due to the high performance nature of the AD7760, correct decoupling and layout techniques are required to obtain the performance as
stated within this data sheet.
Figure 55 shows a simplified connection diagram for the AD7760.
V
IN
A+
V
IN
A–
V
OUT
A–
V
OUT
A+
V
IN
A+
V
IN
A–
V
OUT
A–
V
OUT
A+
DECAPA
DECAPB
V
IN
+
V
IN
–
V
REF+
V
IN
+
V
IN
–
V
REFX
REFGND
R
BIAS
DGND
DGND
DGND
DGND
DGND
DGND
DGND
19
20
21
22
8
30
25
26
10
9
17
1
35
42
43
53
62
64
DB0
DB2
DB1
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB0
DB2
DB1
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
CS
RD/WR
RESET
SYNC
DRDY
MCLK
MCLKGND
CS
RD/WR
RESET
SYNC
DRDY
MCLK
AGND1 AGND1 AGND2 AGND2 AGND2 AGND2 AGND2 AGND3 AGND3 AGND3 AGND3 AGND4
7
34
5
13 16 18 28 23 29 31 32 11
AV
DD
2
AV
DD
2
AV
DD
2
AV
DD
4
AV
DD
1
AV
DD
1
AV
DD
3
AV
DD
2
V
DRIVE
V
DRIVE
DV
DD
PIN 1
4
PIN 1
5
PIN 4 PIN 1
2
PIN 6 PIN 3
3
PIN 2
4
PIN 2
7
PIN 4
4
PIN 6
3
PIN 41
14 15 4 12 6 33 24 27 44 63 41
AD7760BSV
61
60
59
58
55
54
50
49
46
45
40
37
36
38
3
2
57
56
52
51
48
47
39
R19
160kΩ
C64
33pF
C7
100nF
DB [0:15]
U2
AV
DD
3
PIN 24
(VDIF1)
C54
100nF
L6
DV
DD
PIN 41
(DV
DD
)
C58
100nF
L8
AV
DD
2
PIN 4
(RHS)
C48
100nF
L1
PIN 15
(VBIAS)
C50
100nF
L3
PIN 14
(LHS) PIN 27
C62
100nF
L2
L9
AV
DD
4
PIN 12
(VBUF)
C59
10nF
L4
R38
10Ω
AV
DD
1
PIN 5
(VMOD1)
C52
100nF
L5
PIN 33
(VMOD2)
C53
100nF
L11
V
DRIVE
PIN 44
(VDRV1)
C56
100nF
L7
PIN 63
(VDRV2)
C57
100nF
L12
04975-046
Figure 55. Simplified Connection Diagram