Datasheet

AD7760

Rev. A | Page 10 of 36

Pin No. Mnemonic Description

30 DECAPB Decoupling Pin. A 33 pF capacitor must be inserted between this pin and AGND3.

17 R

BIAS

Bias Current Setting Pin. A resistor must be inserted between this pin and AGND. For more details, see the

Bias Resistor Selection section.

45 to 52,

54 to 61

DB15:DB8,

DB7:DB0

16-Bit Bidirectional Data Bus. These are three-state pins that are controlled by the CS pin and the RD/WR

pin. The operating voltage for these pins is determined by the V

DRIVE

voltage. See the Modulator Data

Output Mode

and AD7760 Interface sections for more details.

RESET A falling edge on this pin resets all internal digital circuitry and powers down the part. Holding this pin low

keeps the AD7760 in a reset state.

3 MCLK

Master Clock Input. A low jitter, buffered digital clock must be applied to this pin. The output data rate

depends on the frequency of this clock. See the

Clocking the AD7760 section for more details.

2 MCLKGND Master Clock Ground Sensing Pin.

SYNC Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize

multiple devices in a system. See the

Synchronization section for more details.

RD/WR Read/Write Input. This pin, in conjunction with the chip select pin, is used to read and write data to and

from the AD7760. If this pin is low when CS is low, a read takes place. If this pin is high when CS is low, a

write occurs. See the

Modulator Data Output Mode and AD7760 Interface sections for more details.

DRDY Data Ready Output. Each time new conversion data is available, an active low pulse, ½ ICLK period wide, is

produced on this pin. See the

Modulator Data Output Mode and AD7760 Interface sections for more details.

CS Chip Select Input. Used in conjunction with the RD/WR pin to read and write data from and to the AD7760.

See the Modulator Data Output Mode and AD7760 Interface sections for more details.