Datasheet
AD7760
Rev. A | Page 9 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64
DGND
63
V
DRIVE
62
DGND
61
DB0
60
DB1
59
DB2
58
DB3
57
DB4
56
DB5
55
DB6
54
DB7
53
DGND
52
DB8
51
DB9
50
DB10
49
DB11
47
DB13
46
DB14
45
DB15
42
DGND
43
DGND
44
V
DRIVE
48
DB12
41
DV
DD
40
CS
39
RD/WR
37
RESET
36
SYNC
35
DGND
34
AGND1
33
AV
DD
1
38
DRDY
2
MCLKGND
3
MCLK
4
AV
DD
2
7
AGND1
6
AV
DD
1
5
AGND2
1
DGND
8
DECAPA
9
REFGND
10
V
REF+
12
AV
DD
4
13
AGND2
14
AV
DD
2
15
AV
DD
2
16
AGND2
11
AGND4
PIN 1
17
R
BIAS
18
AGND2
19
V
IN
A+
20
V
IN
A–
21
V
OUT
A–
22
V
OUT
A+
23
AGND3
24
AV
DD
3
25
V
IN
+
26
V
IN
–
27
AV
DD
2
28
AGND2
29
AGND3
30
DECAPB
31
AGND3
32
AGND3
AD7760
TOP VIEW
(Not to Scale)
0
4975-005
Figure 4. 64-Lead TQFP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
6, 33 AV
DD
1
2.5 V Power Supply for Modulator. These pins should be decoupled to AGND1 (Pin 7 and Pin 34, respectively)
with 100 nF and 10 µF capacitors on each pin. See the
Decoupling and Layout Recommendations section
for details.
4, 14, 15, 27 AV
DD
2
5 V Power Supply. These pins should be decoupled to AGND2 (Pin 5 and Pin 13, with 100 nF capacitors
on each of Pin 4, Pin 14, and Pin 15). Pin 27 should be connected to Pin 14 via a 15 nH inductor. See the
Decoupling and Layout Recommendations section for details.
24 AV
DD
3
3.3 V to 5 V Power Supply for Differential Amplifier. This pin should be decoupled to AGND3 (Pin 23) with a
100 nF capacitor. See the
Decoupling and Layout Recommendations section for details.
12 AV
DD
4
3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to Pin 9 with a 10 nF capacitor
in series with a 10 Ω resistor.
7, 34 AGND1 Power Supply Ground for Analog Circuitry Powered by AV
DD
1.
5, 13, 16, 18, 28 AGND2 Power Supply Ground for Analog Circuitry Powered by AV
DD
2.
23, 29, 31, 32 AGND3 Power Supply Ground for Analog Circuitry Powered by AV
DD
3.
11 AGND4 Power Supply Ground for Analog Circuitry Powered by AV
DD
4.
9 REFGND Reference Ground. Ground connection for the reference voltage.
41 DV
DD
2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to DGND with a 100 nF
capacitor.
44, 63 V
DRIVE
Logic Power Supply Input, 1.8 V to 2.5 V. The voltage supplied at these pins determines the operating
voltage of the logic interface. Both of these pins must be connected together and tied to the same supply.
Each pin should also be decoupled to DGND with a 100 nF capacitor.
1, 35, 42, 43,
53, 62, 64
DGND Ground Reference for Digital Circuitry.
19 V
IN
A+ Positive Input to Differential Amplifier.
20 V
IN
A− Negative Input to Differential Amplifier.
21 V
OUT
A− Negative Output from Differential Amplifier.
22 V
OUT
A+ Positive Output from Differential Amplifier.
25 V
IN
+ Positive Input to the Modulator.
26 V
IN
− Negative Input to the Modulator.
10 V
REF+
Reference Input. The input range of this pin is determined by the reference buffer supply voltage (AV
DD
4).
See the
Reference Voltage Filtering section for more details.
8 DECAPA Decoupling Pin. A 100 nF capacitor must be inserted between this pin and AGND.