Datasheet

REV. C
–3–
CONVERTER START TIMING (Figure 1)
J, K, A, B Grades T Grade
Parameter Symbol Min Typ Max Min Typ Max Unit
Conversion Time
8-Bit Cycle (AD674B) t
C
6810 6810 µs
12-Bit Cycle (AD674B) t
C
91215 91215 µs
8-Bit Cycle (AD774B) t
C
456 456 µs
12-Bit Cycle (AD774B) t
C
6 7.3 8 6 7.3 8 µs
STS Delay from CE t
DSC
200 225 ns
CE Pulsewidth t
HEC
50 50 ns
CS to CE Setup t
SSC
50 50 ns
CS Low During CE High t
HSC
50 50 ns
R/C to CE Setup t
SRC
50 50 ns
R/C LOW During CE High t
HRC
50 50 ns
A
0
to CE Setup t
SAC
00ns
A
0
Valid During CE High t
HAC
50 50 ns
READ TIMING—FULL CONTROL MODE (Figure 2)
J, K, A, B Grades T Grade
Parameter Symbol Min Typ Max Min Typ Max Unit
Access Time
C
L
= 100 pF t
DD
1
75 150 75 150 ns
Data Valid After CE Low t
HD
25
2
25
2
ns
20
3
15
4
ns
Output Float Delay t
HL
5
150 150 ns
CS to CE Setup t
SSR
50 50 ns
R/C to CE Setup t
SRR
00ns
A
0
to CE Setup t
SAR
50 50 ns
CS Valid After CE Low t
HSR
00ns
R/C High After CE Low t
HRR
00ns
A
0
Valid After CE Low t
HAR
50 50 ns
NOTES
1
t
DD
is measured with the load circuit of Figure 3a and is defined as the time required
for an output to cross 0.4 V or 2.4 V.
2
0°C to T
MAX
.
3
At –40°C.
4
At –55°C.
5
t
HL
is defined as the time required for the data lines to change 0.5 V when loaded with
the circuit of Figure 3b.
Specifications shown in boldface are tested on all devices at final electrical test with
worst case supply voltages at T
MIN
, 25°C, and T
MAX
. Results from those tests are used
to calculate outgoing quality levels. All min and max specifications are guaranteed,
although only those shown in boldface are tested.
Specifications subject to change without notice.
Parameter Test Conditions Min Max Unit
LOGIC INPUTS
V
IH
High Level Input Voltage 2.0 V
LOGIC
+ 0.5 V
V
IL
Low Level Input Voltage –0.5 +0.8 V
I
IH
High Level Input Current V
IN
= V
LOGIC
–10 +10 µA
I
IL
Low Level Input Current V
IN
= 0 V –10 +10 µA
C
IN
Input Capacitance 10 pF
LOGIC OUTPUTS
V
OH
High Level Output Voltage I
OH
= 0.5 mA 2.4 V
V
OL
Low Level Output Voltage I
OL
= 1.6 mA 0.4 V
I
OZ
High-Z Leakage Current V
IN
= 0 to V
LOGIC
–10 +10 µA
C
OZ
High-Z Output Capacitance 10 pF
DIGITAL SPECIFICATIONS
(For all grades T
MIN
to T
MAX
with V
CC
= +15 V  10% or +12 V  5%, V
LOGIC
= +5 V  10%,
V
EE
= –15 V  10% or –12 V  5%, unless otherwise noted.)
SWITCHING SPECIFICATIONS
(For all grades T
MIN
to T
MAX
with V
CC
= +15 V  10% or +12 V  5%,
V
LOGIC
= +5 V  10%, V
EE
= –15 V  10% or –12 V  5%, unless otherwise noted.)
t
HEC
t
HSC
t
SSC
t
HRC
t
SRC
t
SAC
t
HAC
t
C
t
DSC
CE
CS
R/C
A
0
STS
DB11 – DB0
HIGH
IMPEDANCE
Figure 1. Convert Start Timing
t
SSR
CE
CS
R/C
A
0
STS
DB11 – DB0
t
HSR
t
HRR
t
HAR
t
HD
t
SAR
t
SRR
HIGH
IMPEDANCE
DATA
VA LI D
HIGH
IMPEDANCE
t
HL
t
DD
Figure 2. Read Cycle Timing
DB
N
3k
100pF
DB
N
3k
100pF
5V
HIGH-Z TO LOGIC 0HIGH-Z TO LOGIC 1
High-Z to Logic 1 High-Z to Logic 0
Figure 3a. Load Circuit for Access Time Test
DB
N
3k
100pF
LOGIC 1 TO HIGH-Z
DB
N
3k
100pF
5V
LOGIC 0 TO HIGH-Z
Logic 1 to High-Z Logic 0 to High-Z
Figure 3b. Load Circuit for Output Float Delay Test
AD674B/AD774B