Datasheet

AD7747
Rev. 0 | Page 5 of 28
TIMING SPECIFICATIONS
V
DD
= 2.7 V to 3.6 V, or 4.75 V to 5.25 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = V
DD
; −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
SERIAL INTERFACE
1, 2
See Figure 2
SCL Frequency 0 400 kHz
SCL High Pulse Width, t
HIGH
0.6 μs
SCL Low Pulse Width, t
LOW
1.3 μs
SCL, SDA Rise Time, t
R
0.3 μs
SCL, SDA Fall Time, t
F
0.3 μs
Hold Time (Start Condition), t
HD;STA
0.6 μs After this period, the first clock is generated
Setup Time (Start Condition), t
SU;STA
0.6 μs Relevant for repeated start condition
Data Setup Time, t
SU;DAT
0.1 μs
Setup Time (Stop Condition), t
SU;STO
0.6 μs
Data Hold Time, t
HD;DAT
(Master) 0 μs
Bus-Free Time (Between Stop and Start Condition, t
BUF
) 1.3 μs
1
Sample tested during initial release to ensure compliance.
2
All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
05469-002
SCL
SDA
PS
t
HD;STA
t
LOW
t
R
t
HD;DAT
t
HIGH
t
F
t
SU;DAT
S
t
SU;STA
t
HD;STA
t
SU;STO
P
t
BUF
Figure 2. Serial Interface Timing Diagram