Datasheet

AD7747
Rev. 0 | Page 13 of 28
the bus, allowing another master device to take control of the
bus. Therefore, a master wanting to retain control of the bus
issues successive start conditions known as repeated start
conditions.
AD7747 RESET
To reset the AD7747 without having to reset the entire I
2
C bus,
an explicit reset command is provided. This uses a particular
address pointer word as a command word to reset the part and
upload all default settings. The AD7747 does not respond to the
I
2
C bus commands (do not acknowledge) during the default
values upload for approximately 150 µs (max 200 µs).
The reset command address word is 0xBF.
GENERAL CALL
When a master issues a slave address consisting of seven 0s with
the eighth bit (R/W bit) set to 0, this is known as the general call
address. The general call address is for addressing every device
connected to the I
2
C bus. The AD7747 acknowledges this
address and read in the following data byte.
If the second byte is 0x06, the AD7747 is reset, completely
uploading all default values. The AD7747 does not respond to
the I
2
C bus commands (do not acknowledge) during the default
values upload for approximately 150 µs (200 µs maximum).
The AD7747 does not acknowledge any other general call
commands.
P981–7981–798S
SDATA
SCLOCK
START ADDR ACK ACK DATA ACK STOPSUBADDRESS
1–7
R/W
05469-011
Figure 22. Bus Data Transfer
DATA A(S)S SLAVE ADDR A(S) SUB ADDR A(S)
LSB = 0
LSB = 1
DATA P
S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S) DATA
A(M)
DATA P
WRITE
SEQUENCE
READ
SEQUENCE
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
A(S)
A(M)
05469-012
Figure 23. Write and Read Sequences