Datasheet

AD7745/AD7746
Rev. 0| Page 5 of 28
TIMING SPECIFICATIONS
V
DD
= 2.7 V to 3.6 V, or 4.75 V to 5.25 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = V
DD
; –40°C to +125°C, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
SERIAL INTERFACE
1, 2
See Figure 3
SCL Frequency 0 400 kHz
SCL High Pulse Width, t
HIGH
0.6 µs
SCL Low Pulse Width, t
LOW
1.3 µs
SCL, SDA Rise Time, t
R
0.3 µs
SCL, SDA Fall Time, t
F
0.3 µs
Hold Time (Start Condition), t
HD;STA
0.6 µs After this period, the first clock is generated
Set-Up Time (Start Condition), t
SU;STA
0.6 µs Relevant for repeated start condition
Data Set-Up Time, t
SU;DAT
0.25 µs V
DD
≥ 3.0 V
Data Set-Up Time, t
SU;DAT
0.35 µs V
DD
< 3.0 V
Set-Up Time (Stop Condition), t
SU;STO
0.6 µs
Data Hold Time, t
HD;DAT
(Master) 0 µs
Bus-Free Time (Between Stop and Start Condition, t
BUF
) 1.3 µs
1
Sample tested during initial release to ensure compliance.
2
All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
P
S
t
LOW
t
R
t
F
t
HD:STA
t
HD:DAT
t
SU:DAT
t
SU:STA
t
HD:STA
t
SU:STO
t
HIGH
SCL
PS
SD
A
t
BUF
05468-003
Figure 3. Serial Interface Timing Diagram