Datasheet

REV. 0
–2–
AD7741–SPECIFICATIONS
(V
DD
= +4.75 V to +5.25 V; V
REF
= +2.5 V; f
CLKIN
= 6.144 MHz; all specifications T
MIN
to
T
MAX
unless otherwise noted.)
B and Y Version
1
Parameter
2
Min Typ Max Units Conditions/Comments
DC PERFORMANCE
Integral Nonlinearity
f
CLKIN
= 200 kHz
3
±0.012 % of Span
4
f
CLKIN
= 3 MHz
3
±0.012 % of Span
f
CLKIN
= 6.144 MHz ±0.024 % of Span V
DD
> 4.8 V
Offset Error ±40 mV
Gain Error 0 +0.8 +1.6 % of Span
Offset Error Drift
3
±30 µV/°C
Gain Error Drift
3
±16 ppm of Span/°C
Power Supply Rejection Ratio
3
–63 dB ∆V
DD
= ±5%
ANALOG INPUT
5
Input Current ±50 ±100 nA
Input Voltage Range 0 V
REF
V
+2.5 V REFERENCE (REFIN/OUT)
REFIN
Nominal Input Voltage 2.5 V
Input Impedance
6
N/A
REFOUT
Output Voltage 2.38 2.50 2.60 V
Output Impedance
3
1kΩ
Reference Drift
3
±50 ppm/°C
Line Rejection –60 dB
Reference Noise (0.1 Hz to 10 Hz)
3
100 µV p-p
LOGIC OUTPUT
Output High Voltage, V
OH
4.0 V Output Sourcing 800 µA
7
Output Low Voltage, V
OL
0.4 V Output Sinking 1.6 mA
7
Minimum Output Frequency 0.05 f
CLKIN
Hz V
IN
= 0 V
Maximum Output Frequency 0.45 f
CLKIN
Hz V
IN
= V
REF
LOGIC INPUT
PD ONLY
Input High Voltage, V
IH
2.4 V
Input Low Voltage, V
IL
0.8 V
Input Current ±100 nA
Pin Capacitance 6 10 pF
CLKIN ONLY
Input High Voltage, V
IH
3.5 V
Input Low Voltage, V
IL
0.8 V
Input Current ±2 µA
Pin Capacitance 6 10 pF
CLOCK FREQUENCY
Input Frequency 6.144 MHz For Specified Performance
POWER REQUIREMENTS
V
DD
4.75 5.25 V
I
DD
(Normal Mode) 8 mA Output Unloaded
I
DD
(Power-Down) 15 35 µA
Power-Up Time
3
30 µs Coming Out of Power-Down Mode
NOTES
1
Temperature ranges: B Version –40°C to +85°C: Y Version: –40°C to +105°C.
2
See Terminology.
3
Guaranteed by design and characterization, not production tested.
4
Span = Maximum Output Frequency–Minimum Output Frequency.
5
The absolute voltage on the input pin must not go more positive than V
DD
– 2.25 V or more negative than GND.
6
Because this pin is bidirectional, any external reference must be capable of sinking/sourcing 400 µA in order to overdrive the internal reference.
7
These logic levels apply to CLKOUT only when it is loaded with one CMOS load.
Specifications subject to change without notice.