Datasheet

AD7739 Data Sheet
Rev. A | Page 18 of 32
CHANNEL SETUP REGISTERS
8 Bits, Read/Write Registers, Address 0x28 to
Address 0x2F, Default Value 0x00
These registers are used to configure the selected channel, to
configure its input voltage range, and to set up the corresponding
channel status register (see Table 23 and Table 24).
Table 23. Channel Setup Registers Bits
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic
BUFOFF COM1 COM0 Stat OPT Enable RNG2 RNG1 RNG0
Default
0 0 0 0 0 0 0 0
Table 24. Channel Setup Registers Bit Descriptions
Bit Mnemonic Description
7 BUFOFF Buffer off. If reset to 0, then the internal buffer is enabled. Operation only with the internal buffer enabled is
recommended.
6 to 5 COM1, COM0 Analog inputs configuration.
Channel
COM1 COM0 COM1 COM0
0 0 1 1
0 AIN0 to AINCOM AIN0 to AIN1
1 AIN1 to AINCOM AIN2 to AIN3
2 AIN2 to AINCOM AIN4 to AIN5
3 AIN3 to AINCOM AIN6 to AIN7
4 AIN4 to AINCOM AIN0 to AIN1
5 AIN5 to AINCOM AIN2 to AIN3
6 AIN6 to AINCOM AIN4 to AIN5
7 AIN7 to AINCOM AIN6 to AIN7
4 Stat OPT Status option. When this bit is set to 1, the P0 and P1 bits in the channel status register reflect the state of the
P0 and P1 pins. When this bit is reset to 0, the RDY bit in the channel status register reflect the channel
corresponding to the RDY bit in the ADC status register.
3 Enable Channel enable. Set this bit to 1 to enable the channel in the continuous conversion mode. A single
conversion takes place regardless of the value of this bit.
2 to 0 RNG2 to RNG0 This is the channel input voltage range.
RNG2
RNG1
RNG0
Nominal Input Voltage Range
1 0 0 ±2.5 V
1 0 1 +2.5 V
0 0 0 ±1.25 V
0 0 1 +1.25 V
0 1 0 ±0.625 V
0 1 1 +0.625 V