Datasheet

Data Sheet AD7739
Rev. A | Page 15 of 32
I/O PORT REGISTER
8 Bits, Read/Write Register, Address 0x01,
Default Value 0x30 + Digital Input Value × 0x40
The bits in this register are used to configure and access the
digital I/O port on the AD7739 (see Table 16 and Table 17).
REVISION REGISTER
8 Bits, Read-Only Register, Address 0x02,
Default Value 0x09 + Chip Revision × 0x10
This register contains the 4-bit revision code and the 4-bit
generic code for the ADC (see Table 18 and Table 19). This
register can be used to correctly identify the ADC, or as a check
to ensure that serial communication is working correctly.
TEST REGISTER
24 Bits, Read/Write Register, Address 0x03
This register is used for testing the part in the manufacturing
process. The user must not change the default configuration of
this register.
ADC STATUS REGISTER
8 Bits, Read-Only Register, Address 0x04, Default Value 0x00
In conversion modes, the register bits reflect the individual
channel status. When a conversion is complete, the corresponding
channel data register is updated and the corresponding RDY bit
is set to 1. When the channel data register is read, the corre-
sponding bit is reset to 0. The bit is reset to 0 also when no read
operation has taken place and the result of the next conversion
is being updated to the channel data register. Writing to the
mode register resets all the bits to 0.
In calibration modes, all the register bits are reset to 0 while a
calibration is in progress; all the register bits are set to 1 when
the calibration is complete.
The
RDY
pin output is related to the content of the ADC status
register as defined by the RDYFN bit in the I/O port register.
The RDY0 bit corresponds to Channel 0, the RDY1 bit
corresponds to Channel 1, and so on (see Table 20).
Table 16. I/O Port Register Bits
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic
P0 P1 P0 DIR P1 DIR RDYFN REDPWR 0 Sync
Default
P0 pin P1 pin 1 1 0 0 0 0
Table 17. I/O Port Register Bit Descriptions
Bit Mnemonic Description
7, 6 P0, P1 When the P0 and P1 pins are configured as outputs, the P0 and P1 bits determine the output level of the pin.
When the P0 and P1 pins are configured as inputs, the P0 and P1 bits reflect the current input level on the pins.
5, 4 P0 DIR, P1 DIR These bits determine whether the P0 and P1 pins are configured as inputs or outputs. When set to 1, the
corresponding pin is an input; when reset to 0, the corresponding pin is an output.
3 RDYFN This bit is used to control the function of the
RDY
pin on the AD7739. When this bit is reset to 0, the
RDY
pin
goes low when any channel has unread data. When this bit is set to 1, the
RDY
pin goes low only if all enabled
channels have unread data.
2 REDPWR Reduced power. If this bit is set to 1, the AD7739 works in the reduced power mode. The maximum MCLK
frequency is limited to 4 MHz in the reduced power mode.
1 0 This bit must be 0 for proper operation.
0 Sync This bit enables the
SYNC
pin function. By default, this bit is 0 and
SYNC
/P1 can be used as a digital I/O pin.
When the sync bit is set to 1, the
SYNC
pin can be used to synchronize the AD7739 modulator and digital filter
with other devices in the system.
Table 18. Revision Register Bits
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic
Chip revision code Chip generic code
Default
X X X X 1 0 0 1
Table 19. Revision Register Bit Descriptions
Bit Mnemonic Description
7 to 4 Chip revision code 4-bit factory chip revision code
3 to 0 Chip generic code On the AD7739, these bits read back as 0x09.
Table 20. ADC Status Register Bits
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic
RDY7 RDY6 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0
Default
0 0 0 0 0 0 0 0