Datasheet

REV. 0–4–
AD7738
TIMING SPECIFICATIONS
1, 2, 3
(AV
DD
= 5 V  5%; DV
DD
= 2.7 V to 3.6 V or 5 V  5%; Input Logic 0 = 0 V, Logic 1 = DV
DD
unless otherwise noted.)
Parameter Min Typ Max Unit Test Conditions/Comment
MASTER CLOCK RANGE 1 6.144 MHz
t
1
50 ns SYNC Pulsewidth
t
2
500 ns RESET Pulsewidth
READ OPERATION
t
4
0nsCS Falling Edge to SCLK Falling Edge Setup Time
t
5
4
SCLK Falling Edge to Data Valid Delay
060nsDV
DD
of 4.75 V to 5.25 V
080nsDV
DD
of 2.7 V to 3.3 V
t
5A
4, 5
CS Falling Edge to Data Valid Delay
060nsDV
DD
of 4.75 V to 5.25 V
080nsDV
DD
of 2.7 V to 3.3 V
t
6
50 ns SCLK High Pulsewidth
t
7
50 ns SCLK Low Pulsewidth
t
8
0nsCS Rising Edge after SCLK Rising Edge Hold Time
t
9
6
10 80 ns Bus Relinquish Time after SCLK Rising Edge
WRITE OPERATION
t
11
0nsCS Falling Edge to SCLK Falling Edge Setup
t
12
30 ns Data Valid to SCLK Rising Edge Setup Time
t
13
25 ns Data Valid after SCLK Rising Edge Hold Time
t
14
50 ns SCLK High Pulsewidth
t
15
50 ns SCLK Low Pulsewidth
t
16
0nsCS Rising Edge after SCLK Rising Edge Hold Time
NOTES
1
Sample tested during initial release to ensure compliance.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.6 V.
3
See Figures 1 and 2.
4
These numbers are measured with the load circuit of Figure 3 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
5
This specification is relevant only if CS goes low while SCLK is low.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 3.
The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing
characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications are subject to change without notice.