Datasheet

REV. 0
AD7738
–3–
Parameter Min Typ Max Unit Test Conditions/Comment
LOGIC INPUTS
SCLK, DIN, CS, and RESET Inputs
Input Current ± 1 µA
Input Current CS ± 10 µA CS = AV
DD
–40 µA Internal Pull-Up Resistor
Input Capacitance 4 pF
V
T+
1
1.4 2 V DV
DD
= 5 V
V
T–
1
0.8 1.4 V DV
DD
= 5 V
V
T+
– V
T–
1
0.3 0.85 V DV
DD
= 5 V
V
T+
1
0.95 2 V DV
DD
= 3 V
V
T–
1
0.4 1.1 V DV
DD
= 3 V
V
T+
– V
T–
1
0.3 0.85 V DV
DD
= 3 V
MCLK IN Only
Input Current ± 10 µA
Input Capacitance 4 pF
V
INL
Input Low Voltage 0.8 V DV
DD
= 5 V
V
INH
Input High Voltage 3.5 V DV
DD
= 5 V
V
INL
Input Low Voltage 0.4 V DV
DD
= 3 V
V
INH
Input High Voltage 2.5 V DV
DD
= 3 V
LOGIC OUTPUTS
MCLKOUT
10
, DOUT, RDY
V
OL
Output Low Voltage 0.4 V I
SINK
= 800 µA, DV
DD
= 5 V
V
OH
Output High Voltage 4.0 V I
SOURCE
= 200 µA, DV
DD
= 5 V
V
OL
Output Low Voltage 0.4 V I
SINK
= 100 µA, DV
DD
= 3 V
V
OH
Output High Voltage DV
DD
– 0.6 V I
SOURCE
= 100 µA, DV
DD
= 3 V
Floating State Leakage Current ± 1 µA
Floating State Leakage Capacitance 3 pF
P1 INPUT Levels Referenced to Analog Supplies
Input Current ± 10 µA
V
INL
Input Low Voltage 0.8 V AV
DD
= 5 V
V
INH
Input High Voltage 3.5 V AV
DD
= 5 V
P0, P1 OUTPUT
V
OL
Output Low Voltage 0.4 V I
SINK
= 8 mA, T
MAX
= 70°C, AV
DD
= 5 V
0.4 V I
SINK
= 5 mA, T
MAX
= 85°C, AV
DD
= 5 V
0.4 V I
SINK
= 2.5 mA, T
MAX
= 105°C, AV
DD
= 5 V
V
OH
Output High Voltage 4.0 V I
SOURCE
= 200 µA, AV
DD
= 5 V
POWER REQUIREMENTS
AV
DD
– AGND Voltage 4.75 5.25 V
DV
DD
– DGND Voltage 4.75 5.25 V
2.70 3.60 V
AV
DD
Current (Normal Mode) 13.6 16 mA AV
DD
= 5 V
AV
DD
Current (Internal Buffer Off ) 8.5 mA AV
DD
= 5 V
DV
DD
Current (Normal Mode)
11
2.7 3 mA DV
DD
= 5 V
DV
DD
Current (Normal Mode)
11
1.0 1.5 mA DV
DD
= 3 V
AV
DD
+ DV
DD
Current (Standby Mode)
12
80 µAAV
DD
= DV
DD
= 5 V
Power Dissipation (Normal Mode)
11
85 100 mW
Power Dissipation (Standby Mode)
12
500 µWAV
DD
= DV
DD
= 5 V
NOTES
1
Specifications are not production tested, but guaranteed by design and/or characterization data at initial product release.
2
Specifications before calibration. Channel System Calibration reduces these errors to the order of the noise.
3
Applies after the Zero Scale and Full-Scale calibration. The Negative Full Scale error represents the remaining error after removing the offset and gain error.
4
Specifications before calibration. ADC Zero Scale Self-Calibration or Channel Zero Scale System Calibration reduces this error to the order of the noise.
5
The output data span corresponds to the Nominal (Typical) Input Voltage Range. Correct operation of the ADC is guaranteed within the specified min/max.
Outside the Nominal Input Voltage Range, the OVR bit in the Channel Status register is set and the Channel Data register value depends on CLAMP bit in the
Mode register. See the register description and circuit description for more details.
6
If chopping is enabled or when switching between channels, there will be a dynamic current charging the capacitance of the multiplexer, capacitance of the pins,
and any additional capacitance connected to the MUXOUT. See the circuit description for more details.
7
For specified performance. Part is functional with Lower V
REF
8
Dynamic current charging the sigma-delta modulator input switching capacitor.
9
Outside the specified calibration range, calibration is possible but the performance may degrade.
10
These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load.
11
With external MCLK, MCLKOUT disabled (CLKDIS bit set in the Mode reg ister).
12
External MCLKIN = 0 V or DV
DD
, Digital Inputs = 0 V or DV
DD
, P0 and P1 = 0 V or AV
DD
.
Specifications are subject to change without notice.