Datasheet

REV. 0–14–
AD7738
I/O Port Register
8 Bits, Read/Write Register, Address 01h, Default Value 30h + Digital Input Value  40h
The bits in this register are used to configure and access the digital I/O pin on the AD7738.
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic P0 P1 P0 DIR P1 DIR RDY FN 0 0 SYNC
Default P0 Pin P1 Pin 1 1 0 0 0 0
Bit Mnemonic Description
7P0 When the AINCOM/P0 pin is configured as a digital output, the P0 bit determines the pin’s output level.
6P1When the P1 pin is configured as an output, the P1 bit determines the pin’s output level. When the P1
pin is configured as an input, the P1 bit reflects the current input level on the pin.
5 P0 DIRWhen set to 1, the AINCOM/P0 pin is configured as an analog input. When set to 0, the AINCOM/P0
pin is configured as a digital output.
4 P1 DIRThis bit determines whether P1 pin is configured as an input or an output. When set to 1, the P1 pin will
be a digital input; when reset to 0, the pin will be a digital output.
3 RDY FN This bit is used to control the function of the RDY pin on the AD7738. When this bit is reset to 0 the RDY
pin goes low when any channel has unread data. When this bit is set to 1, the RDY pin will only go low if all
enabled channels have unread data.
2, 1 0 These bits must be zero for proper operation.
0 SYNC This bit enables the SYNC pin function. By default, this bit is 0 and SYNC/P1 can be used as a
digital I/O pin. When the SYNC EN bit is set to 1, the SYNC pin can be used to synchronize the
AD7738 modulator and digital filter with other devices in the system.
Revision Register
8 Bits, Read-Only Register, Address 02h, Default Value 01h + Chip Revision  10h
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic Chip Revision Code Chip Generic Code
Default x x x x 0 0 0 1
Bit Mnemonic Description
7–4 Chip Revision Code 4-Bit Factory Chip Revision Code
3–0 Chip Generic Code On the AD7738, these bits will read back as 01h.
Test Register
24 Bits, Read/Write Register, Address 03h
This register is used for testing the part in the manufacturing process. The user must not change the default configuration of this register.
ADC Status Register
8 Bits, Read-Only Register, Address 04h, Default Value 00h
In conversion modes, the register bits reflect the individual channel status. When a conversion is complete, the corresponding Channel
Data register is updated and the corresponding RDY bit is set to 1. When the Channel Data register is read, the corresponding bit is
reset to 0. The bit is also reset to 0 when no read operation has taken place and the result of the next conversion is being updated to
the Channel Data register. Writing to the Mode register resets all the bits to 0.
In calibration modes, all the register bits are reset to 0 while a calibration is in progress and all the bits are set to 1 when the
calibration is complete.
The RDY pin output is related to the content of ADC Status register as defined by the RDY Function bit in the I/O Port register.
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic RDY7 RDY6 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0
Default 0 0 0 0 0 0 0 0
The RDY0 bit corresponds to Channel 0, RDY1 bit to Channel 1, and so on.