Datasheet

REV. 0

AD7738

–13–

The AD7738 is configurable through a series of registers. Some of them configure and control general AD7738 features, others are

specific to each channel. The register data widths vary from 8 bits to 24 bits. All registers are accessed through the Communi

cation

register, i.e., any communication to the AD7738 must start with a write to the Communication register, specifying which register

will be subsequently read or written.

Communications Register

8 Bits, Write-Only Register, Address 00h

All communications to the part must start with a write operation to the Communications register. The data written to the Commu-

nications register determines whether the subsequent operation will be a read or write and to which register this operation will be

directly placed.

The digital interface defaults to expect write operation to the Communication register after power on, after reset, or

after the subsequent read or write operation to the selected register is complete. If the interface sequence is lost, the part can be reset

by writing at least 32 serial clock cycles with DIN high and CS low (Note that all of the parts including modulator, filter, interface

and all registers are reset in this case). Remember to keep DIN low while reading 32 or more bits either in Continuous Read mode or

with the DUMP bit and “24/16” bit in the Mode register set.

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic 0 R/W 6-Bit Register Address

Bit Mnemonic Description

70 This bit must be zero for proper operation.

6R/W A zero in this bit indicates that the next operation will be a write to a specified register.

A one in this bit indicates that the next operation will be a read from a specified register.

5–0 Address Address specifying to which register the read or write operation will be directed.

For channel specific registers the three LSBs, i.e., Bit 2, Bit 1, and Bit 0, specify the channel number.

When the subsequent operation writes to the Mode register, then the three LSBs specify the channel

selected for operation determined by the Mode register value. See Table X.

(The analog input’s configuration depends on the COM1, COM0 bits in the Channel Setup register.)

Table X.

Bit 2 Bit 1 Bit 0 Channel Single Input Differential Input

0000 AIN0 AIN0–AIN1

0011 AIN1 AIN2–AIN3

0102 AIN2 AIN4–AIN5

0113 AIN3 AIN6–AIN7

1004 AIN4 AIN0–AIN1

1015 AIN5 AIN2–AIN3

1106 AIN6 AIN4–AIN5

1117 AIN7 AIN6–AIN7