Datasheet

Data Sheet AD7734
Rev. A | Page 5 of 32
Parameter Min Typ Max Unit Test Conditions/Comments
Power Dissipation (Normal Mode)
13
85 100 mW
AV
DD
+DV
DD
Current (Standby Mode)
14
100 µA
Power Dissipation (Standby Mode)
14
525 µW
1
Specifications are not production tested but guaranteed by design and/or characterization data at initial product release.
2
See Typical Performance Characteristics.
3
Specifications before calibration. Channel system calibration reduces these errors to the order of the noise.
4
Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error.
5
ADC zero-scale self-calibration reduces this error to ±10 mV. Channel zero-scale system calibration reduces this error to the order of the noise.
6
For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage
range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register
value depends on the CLAMP bit in the mode register. See the register and circuit descriptions for more details.
7
The adjacent channels are not affected by AIN voltage up to ±16.5 V.
8
Pin impedance is from the pin to the internal node. In normal circuit configuration, the analog input total impedance is typically 108.5 kΩ + 15.5 kΩ = 124 kΩ.
9
For specified performance. Part is functional with lower V
REF
.
10
Dynamic current charging the sigma-delta modulator input switching capacitor.
11
Outside the specified calibration range, calibration is possible but the performance may degrade.
12
These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load.
13
With external MCLK, MCLKOUT disabled (CLKDIS bit set in the mode register).
14
External MCLKIN = 0 V or DV
DD
, digital inputs = 0 V or DV
DD
, P0 and P1 = 0 V or AV
DD
.