Datasheet

AD7731
–18–
REV. 0
Bit Bit
Location Mnemonic Description
MR3 BO Burnout Current Bit. A 1 in this bit activates the burnout currents. When active, the burnout
currents connect to the selected analog input pair, one source current to the AIN(+) input
and one sink current to the AIN(–) input. A 0 in this bit turns off the on-chip burnout
currents.
MR2–MR0 CH2–CH0 Channel Select. These three bits select a channel either for conversion or for access to cali-
bration coefficients as outlined in Table XIII. There are three pairs of calibration registers on
the part. In fully differential mode, the part has three input channels so each channel has its
own pair of calibration registers. In pseudo-differential mode, the AD7731 has five input
channels with some of the input channel combinations sharing calibration registers. With
CH2, CH1 and CH0 at a logic 1, the part looks at the AIN6 input internally shorted to itself.
This can be used as a test method to evaluate the noise performance of the part with no ex-
ternal noise sources. In this mode, the AIN6 input should be connected to an external volt-
age within the allowable common-mode range for the part. The power-on/default status of
these bits is 1, 0, 0.
Table XIII. Channel Selection
CH2 CH1 CH0 AIN(+) AIN(–) Type Calibration Register Pair
0 0 0 AIN1 AIN6 Pseudo Differential Register Pair 0
0 0 1 AIN2 AIN6 Pseudo Differential Register Pair 1
0 1 0 AIN3 AIN6 Pseudo Differential Register Pair 2
0 1 1 AIN4 AIN6 Pseudo Differential Register Pair 2
1 0 0 AIN1 AIN2 Fully Differential Register Pair 0
1 0 1 AIN3 AIN4 Fully Differential Register Pair 1
1 1 0 AIN5 AIN6 Fully Differential Register Pair 2
1 1 1 AIN6 AIN6 Test Mode Register Pair 2
Filter Register (RS2-RS0 = 0, 1, 1); Power-On/Reset Status: 2002 Hex
The Filter Register is a 16-bit register from which data can either be read or to which data can be written. This register determines
the amount of averaging performed by the filter and the mode of operation of the filter. It also sets the chopping mode. Table XIV
outlines the bit designations for the Filter Register. FR0 through FR15 indicate the bit location, FR denoting the bits are in the Filter
Register. FR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a flowchart for writing to the registers
on the part.
Table XIV. Filter Register
51RF41RF31RF21RF11RF01RF9RF8RF
)0(11FS)0(01FS)1(9FS)0(8FS)0(7FS)0(6FS)0(5FS)0(4FS
7RF6RF5RF4RF3RF2RF1RF0RF
)0(3FS)0(2FS)0(1FS)0(0FS)0(OREZ)0(PHC)1(PIKS)0(TSAF
Bit Bit
Location Mnemonic Description
FR15–FR4 SF11–SF0 Sinc
3
Filter Selection Bits. The AD7731 contains two filters, a Sinc
3
filter and an FIR filter.
The 12 bits programmed to SF11 through SF0 sets the amount of averaging which the Sinc
3
filter performs. As a result, the number programmed to these 12 bits affects the –3 dB fre-
quency and output update rate from the part (see Filter Architecture section). The allowable
range for SF words depends on whether the part is operated with CHP on or off and SKIP
on or off. Table XV outlines the SF ranges for different setups.
REV. A