Datasheet

AD7731
–11–REV. 0
Output Noise (CHP = 1, SKIP = 0)
Table III shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7731 when used in
chopping mode (CHP of Filter Register = 1) and with the second filter included in the loop. The numbers are generated with a mas-
ter clock frequency of 4.9152 MHz. These numbers are typical and generated at a differential analog input voltage of 0 V. The out-
put update rate is selected via the SF0 to SF11 bits of the Filter Register. Table IV, meanwhile, shows the output peak-to-peak
resolution in bits (rounded to the nearest 0.5 LSB) for the same output update rates. It is important to note that the numbers in
Table IV represent the resolution for which there will be no code flicker within a six-sigma limit. They are not calculated based on
rms noise but on peak-to-peak noise.
The numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the
same as the equivalent bipolar input range. As a result, the numbers in Table III will remain the same for unipolar ranges. To calcu-
late the number for Table IV for unipolar input ranges simply subtract one from the peak-to-peak resolution number in bits.
Table III. Output Noise vs. Input Range and Update Rate (CHP = 1, SKIP = 0)
Typical Output RMS Noise in nV
Output –3 dB SF Settling Time Input Range
Data Rate Frequency Word Normal Fast Step 61.28 V 6640 mV 6320 mV 6160 mV 680 mV 640 mV 620 mV
50 Hz 1.97 Hz 2048 440 ms 40 ms 700 425 265 170 120 85 55
100 Hz 3.95 Hz 1024 220 ms 20 ms 980 550 330 230 190 115 90
150 Hz 5.92 Hz 683 147 ms 13.3 ms 1230 700 445 270 210 140 100
200 Hz 7.9 Hz 512 110 ms 10 ms 1260 840 500 340 245 170 105
400 Hz 15.8 Hz 256 55 ms 5 ms 2000 1230 690 430 335 215 160
800 Hz 31.6 Hz 128 27.5 ms 2.5 ms 3800 2100 1400 760 590 345 220
Table IV. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 1, SKIP = 0)
Peak-to-Peak Resolution in Bits
Output –3 dB SF Settling Time Input Range
Data Rate Frequency Word Normal Fast Step 61.28 V 6640 mV 6320 mV 6160 mV 680 mV 640 mV 620 mV
50 Hz 1.97 Hz 2048 440 ms 40 ms 19 19 18.5 18.5 18 17.5 17
100 Hz 3.95 Hz 1024 230 ms 30 ms 19 18.5 18.5 18 17 17 16
150 Hz 5.92 Hz 683 147 ms 13.3 ms 18.5 18 18 17.5 17 16.5 16
200 Hz 7.9 Hz 512 110 ms 10 ms 18.5 18 17.5 17.5 17 16.5 16
400 Hz 15.8 Hz 256 55 ms 5 ms 17.5 17.5 17 17 16.5 16 15.5
800 Hz 31.6 Hz 128 27.5 ms 2.5 ms 17 16.5 16 16 15.5 15 15
ON-CHIP REGISTERS
The AD7731 contains 12 on-chip registers that can be accessed
via the serial port of the part. These registers are summarized in
Figure 4 and in Table V, and described in detail in the following
sections.
RS2 RS1 RS0
REGISTER
SELECT
DECODER
STATUS REGISTER
DATA REGISTER
MODE REGISTER
FILTER REGISTER
OFFSET REGISTER (x3)
GAIN REGISTER (x3)
TEST REGISTER
COMMUNICATIONS REGISTER
DINDIN
DIN
DIN
DIN
DIN
DIN
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
Figure 4. Register Overview
REV. A