a Low Noise, High Throughput 24-Bit Sigma-Delta ADC AD7731 GENERAL DESCRIPTION FEATURES 24-Bit Sigma-Delta ADC 16 Bits p-p Resolution at 800 Hz Output Rate Programmable Output Rates up to 6.4 kHz Programmable Gain Front End 60.0015% Nonlinearity Buffered Differential Inputs Programmable Filter Cutoffs FASTStep™* Mode for Channel Sequencing Single Supply Operation The AD7731 is a complete analog front-end for process control applications.
(AVDD = +5 V, DVDD = +3 V or +5 V; REF IN(+) = +2.5 V; REF IN(–) = AGND; AGND = CLK IN = 4.9152 MHz. All specifications TMIN to TMAX unless otherwise noted.) AD7731–SPECIFICATIONS DGND = 0 V; f Parameter STATIC PERFORMANCE (CHP = 0) No Missing Codes2 Output Noise and Update Rates2 Integral Nonlinearity Offset Error2 Offset Drift vs. Temperature2 Offset Drift vs. Time5 Positive Full-Scale Error2, 6 Positive Full-Scale Drift vs. Temp2, 7, 8 Positive Full-Scale Drift vs. Time5 Gain Error2, 9 Gain Drift vs.
AD7731 B Version1 Units AGND + 1.2 V AVDD – 0.95 V V min V max +2.5 +5 5.5 10 AGND – 30 mV AVDD + 30 mV 0.3 0.65 V nom V nom µA max µA max V min V max V min V max ± 10 µA max 0.8 0.4 2.0 V max V max V min DVDD = +5 V DVDD = +3 V 1.4/3 0.95/2.5 0.8/1.4 0.4/1.1 0.4/0.85 0.4/0.8 V min/V max V min/V max V min/V max V min/V max V min/V max V min/V max DVDD = +5 V DVDD = +3 V DVDD = +5 V DVDD = +3 V DVDD = +5 V DVDD = +3 V 0.8 0.4 3.5 2.
AD7731 NOTES 1 Temperature Range: –40°C to +85°C. 2 Sample tested during initial release. 3 No missing codes performance with CHP = 0 and SKIP = 1 is 22 bits. 4 The offset (or zero) numbers with CHP = 0 can be up to 1 mV precalibration. Internal zero-scale calibration reduces this to 2 µV typical. Offset numbers with CHP = 1 are typically 3 µV precalibration. Internal zero-scale calibration reduces this by about 1 µV.
AD7731 ABSOLUTE MAXIMUM RATINGS* Plastic DIP Package, Power Dissipation........................450 mW θJA Thermal Impedance ............................................... 105°C/W Lead Temperature (Soldering, 10 sec) ............................ +260°C TSSOP Package, Power Dissipation..............................450 mW θJA Thermal Impedance ............................................... 128°C/W Lead Temperature, Soldering Vapor Phase (60 sec) ......................................................
AD7731 BUFFER AMPLIFIER BURNOUT CURRENTS TWO 100nA BURNOUT CURRENTS ALLOW THE USER TO EASILY DETECT IF A TRANSDUCER HAS BURNT OUT OR GONE OPEN-CIRCUIT THE BUFFER AMPLIFIER PRESENTS A HIGH IMPEDANCE INPUT STAGE FOR THE ANALOG INPUTS ALLOWING SIGNIFICANT EXTERNAL SOURCE IMPEDANCES PROGRAMMABLE DIGITAL FILTER PROGRAMMABLE GAIN AMPLIFIER DIFFERENTIAL REFERENCE THE PROGRAMMABLE GAIN AMPLIFIER ALLOWS SEVEN UNIPOLAR AND SEVEN BIPOLAR INPUT RANGES FROM +20mV TO +1.
AD7731 SINC3 FILTER INPUT CHOPPING CHOPPING DISABLED THE FIRST STAGE OF THE DIGITAL FILTERING ON THE PART IS THE SINC3 FILTER. THE OUTPUT UPDATE RATE AND BANDWIDTH OF THIS FILTER CAN BE PROGRAMMED. IN SKIP MODE, THE SINC3 FILTER IS THE ONLY FILTERING PERFORMED SEE PAGE 25 ON THE P3T. THE ANALOG INPUT TO THE PART CAN BE CHOPPED. IN CHOPPING MODE, THE INPUT IS CHOPPEDAND THE OUTPUT OF THE FIRST STAGE FILTER IS CHOPPED REMOVING ERRORS IN THAT PATH.
AD7731 PIN FUNCTION DESCRIPTIONS (Continued) Pin No. Pin Mnemonic 3 MCLK OUT 4 POL 5 SYNC 6 RESET 7 8 9 10 NC AGND AVDD AIN1 11 AIN2 12 AIN3/D1 13 AIN4/D0 14 REF IN(+) 15 REF IN(–) 16 AIN5 17 AIN6 18 STANDBY 19 CS Function When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN and MCLK OUT. If an external clock is applied to the MCLK IN, MCLK OUT provides an inverted clock signal.
AD7731 PIN FUNCTION DESCRIPTIONS (Continued) Pin No. Pin Mnemonic 20 RDY 21 DOUT 22 DIN 23 24 DVDD DGND Function Logic output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a logic low on this output indicates that a new output word is available from the AD7731 data register. The RDY pin will return high upon completion of a read operation of a full output word.
AD7731 OUTPUT NOISE AND RESOLUTION SPECIFICATION The AD7731 has a number of different modes of operation of the on-chip filter and chopping features. These options are discussed in more detail in later sections. The part can be programmed either to optimize the throughput rate and settling time or to optimize noise and drift performance. Noise tables for two of the primary modes of operation of the part are outlined below for a selection of output rates and settling times.
AD7731 Output Noise (CHP = 1, SKIP = 0) Table III shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7731 when used in chopping mode (CHP of Filter Register = 1) and with the second filter included in the loop. The numbers are generated with a master clock frequency of 4.9152 MHz. These numbers are typical and generated at a differential analog input voltage of 0 V. The output update rate is selected via the SF0 to SF11 bits of the Filter Register.
AD7731 Table V.
AD7731 Communications Register (RS2-RS0 = 0, 0, 0) The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the Communications Register. The data written to the Communications Register determines whether the next operation is a read or write operation, the type of read operation and to which register this operation takes place.
AD7731 Bit Location Bit Mnemonic Description CR3 ZERO A zero must be written to this bit to ensure correct operation of the AD7731. CR2-CR0 RS2-RS0 Register Selection Bits. RS2 is the MSB of the three selection bits. The three bits select to which one of eight on-chip registers the next read or write operation takes place as shown in Table VIII. Table VIII.
AD7731 Data Register (RS2-RS0 = 0, 0, 1); Power On/Reset Status: 000000 Hex The Data Register on the part is a read-only register that contains the most up-to-date conversion result from the AD7731. Figure 5 shows a flowchart for reading from the registers on the AD7731. The register can be programmed to be either 16 or 24 bits wide, determined by the status of the WL bit of the Mode Register. The RDY output and RDY bit of the Status Register are set low when the Data Register is updated.
AD7731 MD2 MD1 MD0 Operating Mode 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Sync (Idle) Mode. In this mode, the modulator and filter are held in reset mode and the AD7731 is not processing any new samples or data. Placing the part in this mode is equivalent to exerting the SYNC input pin. However, exerting the SYNC does not actually force these mode bits to 0, 0, 0. The part returns to this mode after a calibration or after a conversion in Single Conversion Mode.
AD7731 Bit Location Bit Mnemonic MR12 B/U MR11 DEN MR10–MR9 D1–D0 MR8 WL MR7 HIREF MR6–MR4 RN2–RN0 Description Bipolar/Unipolar Bit. A 0 in this bit selects bipolar operation and the output coding is 00...000 for negative full-scale input, 10...000 for zero input and 11...111 for positive fullscale input. A 1 in this bit selects unipolar operation and the output coding is 00...000 for zero input and 11...111 for positive full-scale input. Digital Output Enable Bit.
AD7731 Bit Location Bit Mnemonic MR3 BO Burnout Current Bit. A 1 in this bit activates the burnout currents. When active, the burnout currents connect to the selected analog input pair, one source current to the AIN(+) input and one sink current to the AIN(–) input. A 0 in this bit turns off the on-chip burnout currents. MR2–MR0 CH2–CH0 Channel Select. These three bits select a channel either for conversion or for access to calibration coefficients as outlined in Table XIII.
AD7731 Table XV. SF Ranges CHOP SKIP SF Range Output Update Rate Range (Assuming 4.9152 MHz Clock) 0 1 0 1 0 0 1 1 2048 to 150 2048 to 75 2048 to 40 2048 to 20 150 Hz to 2.048 kHz 50 Hz to 1.365 kHz 150 Hz to 7.6 kHz 50 Hz to 5.12 kHz Bit Location Bit Mnemonic FR3 FR2 ZERO CHP FR1 SKIP FR0 FAST Description A zero must be written to this bit to ensure correct operation of the AD7731. Chop Enable Bit. This bit determines if the chopping mode on the part is enabled.
AD7731 READING FROM AND WRITING TO THE ON-CHIP REGISTERS The AD7731 contains a total of twelve on-chip registers. These registers are all accessed over a three-wire interface. As a result, addressing of registers is via a write operation to the topmost register on the part, the Communications Register. Figure 5 shows a flowchart for reading from the different registers on the part summarizing the sequence and the words to be written to access each of the registers.
AD7731 CALIBRATION OPERATION SUMMARY The AD7731 contains a number of calibration options as outlined previously. Table XVI summarizes the calibration types, the operations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to monitor the hardware RDY pin using either interrupt-driven or polling routines. The second method is to do a software poll of the RDY bit in the Status Register.
AD7731 CIRCUIT DESCRIPTION The AD7731 is a sigma-delta A/D converter with on-chip digital filtering, intended for the measurement of wide dynamic range, low-frequency signals such as those in strain-gage, pressure transducer, temperature measurement, industrial control or process control applications. It contains a sigma-delta (or chargebalancing) ADC, a calibration microcontroller with on-chip static RAM, a clock oscillator, a digital filter and a bidirectional serial communications port.
AD7731 ANALOG INPUT Analog Input Channels The AD7731 has six analog input pins (labelled AIN1 to AIN6) which can be configured as either three fully differential input channels or five pseudo-differential input channels. Bits CH0, CH1 and CH2 of the Mode Register configure the input channel arrangement and the channel selection is as outlined previously in Table XIII.
AD7731 REFERENCE INPUT SIGMA-DELTA MODULATOR The AD7731’s reference inputs, REF IN(+) and REF IN(–), provide a differential reference input capability. The commonmode range for these differential inputs is from AGND to AVDD. The nominal reference voltage, VREF (REF IN(+) – REF IN(–)), for specified operation is +2.5 V with the HIREF bit at 0 and +5 V with the HIREF bit at 1. The part is also functional with VREF of +2.5 V with the HIREF bit at 1. This results in a halving of all input ranges.
AD7731 0 The operation mode can be changed to achieve optimum performance in various applications. The CHP bit should generally be set to 0 when using the AD7731 in applications where higher throughput rates are a concern or in applications where the reduced rejection at the chopping frequency in chop mode is an issue. The part should be operated with CHP = 1 when drift, noise rejection and optimum EMI rejection are important criteria in the application.
AD7731 Chop Mode (SKIP = 0, CHP = 1) With CHOP mode enabled and SKIP mode disabled, the second stage filter is presented with alternating first stage filter outputs and processes data accordingly. It has two primary functions. One is to set the overall frequency response and the second is to eliminate the modulated offset effect which appears on the output of the first stage filter. Time to first output is 22 × 1/Output Rate in this mode.
AD7731 Nonchop Mode (SKIP = 0, CHP = 0) With CHOP mode disabled and SKIP mode disabled, the only function of the second stage filter is to give the overall frequency response. Figure 11 shows the frequency response for the AD7731 with the second stage filter is set for normal FIR operation, chop mode disabled, the decimal equivalent of the word in the SF bits set to 1536 and a master clock frequency of 4.9152 MHz.
AD7731 FASTStep™ Mode (SKIP = 0, FAST = 1) The second mode of operation of the second stage filter is in FASTStep™ mode which enables it to respond rapidly to step inputs even when the second stage filter is in the loop. The FASTStep™ mode is not relevant with SKIP mode enabled. The FASTStep™ mode is enabled by placing a 1 in the FAST bit of the Filter Register. If the FAST bit is 0, the part continues to process step inputs with the normal FIR filter as the second stage filter.
AD7731 CALIBRATION The AD7731 provides a number of calibration options that can be programmed via the MD2, MD1 and MD0 bits of the Mode Register. The different calibration options are outlined in the Mode Register and Calibration Operations sections. A calibration cycle may be initiated at any time by writing to these bits of the Mode Register. Calibration on the AD7731 removes offset and gain errors from the device.
AD7731 Internal Full-Scale Calibration An internal full-scale calibration is initiated on the AD7731 by writing the appropriate values (1, 0, 1) to the MD2, MD1 and MD0 bits of the Mode Register. In this calibration mode, the full-scale point used in determining the calibration coefficients is with an internally-generated full-scale voltage.
AD7731 The system full-scale calibration needs to be performed as one part of a two part full calibration. However, once a full calibration has been performed, additional system full-scale calibrations can be performed by themselves to adjust the part’s gain calibration point only. When performing a two-step full calibration, care should be taken as to the sequence in which the two steps are performed.
AD7731 USING THE AD7731 Clocking and Oscillator Circuit The AD7731 requires a master clock input, which may be an external CMOS compatible clock signal applied to the MCLK IN pin with the MCLK OUT pin left unconnected. Alternatively, a crystal or ceramic resonator of the correct frequency can be connected between MCLK IN and MCLK OUT in which case the clock circuit will function as an oscillator, providing the clock source for the part.
AD7731 Placing the part in standby mode reduces the total current to 10 µA typical when the part is operated from an external master clock, provided this master clock is stopped. If the external clock continues to run in standby mode, the standby current increases to 400 µA typical. If a crystal or ceramic resonator is used as the clock source, then the total current in standby mode is 400 µA typical. This is because the on-chip oscillator circuit continues to run when the part is in its standby mode.
AD7731 SERIAL INTERFACE The AD7731’s programmable functions are controlled via a set of on-chip registers. Access to these registers is via the part’s serial interface. After power-on or RESET, the device expects a write to its Communications Register. The data written to this register determines whether the next operation to the part is a read or a write operation and also determines to which register this read or write operation occurs.
AD7731 Read Operation The reading of data from the part is from an output shift register. On initiation of a read operation, data is transferred from the specified register to the output shift register. This is a parallel shift and is transparent to the user. Figure 16 shows a timing diagram for a read operation from the output shift register of the AD7731. With the POL input at a logic high, the data is clocked out of the output shift register on the falling edge of SCLK.
AD7731 CONFIGURING THE AD7731 The AD7731 contains twelve on-chip registers which can be accessed via the serial interface. Figure 5 and Figure 6 have outlined a flowchart for the reading and writing of these registers. Table XIX and Table XX outline sample pseudo-code for some commonly used routines. The required operating conditions will dictate the values loaded to the Mode and Filter Registers. The values given here are for example purposes only. Table XIX.
AD7731 MICROCOMPUTER/MICROPROCESSOR INTERFACING The AD7731’s flexible serial interface allows for easy interface to most microcomputers and microprocessors. The pseudo-code of Table XVIII and Table XIX outline typical sequences for interfacing a microcontroller or microprocessor to the AD7731. Figures 18, 19 and 20 show some typical interface circuits. The serial interface on the AD7731 has the capability of operating from just three wires and is compatible with SPI interface protocols.
AD7731 The 8XC51 is configured in its Mode 0 serial interface mode. Its serial interface contains a single data line. As a result, the DATA OUT and DATA IN pins of the AD7731 should be connected together. This means that the AD7731 must not be configured for continuous read operation when interfacing to the 8XC51. The serial clock on the 8XC51 idles high between data transfers and, therefore, the POL input of the AD7731 should be hard-wired to a logic high.
AD7731 APPLICATIONS Data Acquisition The on-chip PGA allows the AD7731 to handle analog input voltage ranges from 20 mV to 1.28 V. This makes the AD7731 suitable for a range of application areas from handling signals directly from a transducer to processing fully-conditioned fullscale inputs. Some of these applications are discussed in the following sections.
AD7731 Figure 24 shows another temperature measurement application for the AD7731. In this case, the temperature transducer is an RTD (Resistive Temperature Device), a PT100. The arrangement is a four-lead RTD configuration. There are voltage drops across lead resistances RL1 and RL4 and across resistor R2 but these simply shift the common-mode voltage. Resistor R2 is required to set the common-mode voltage within the allowable range for the AD7731.
AD7731 +5V AVDD DVDD AVDD AD7731 100nA THERMOCOUPLE JUNCTION R AIN1 SIGMA-DELTA A/D CONVERTER AIN2 C C AIN3 AIN4 AIN5 SWITCHING MATRIX R PGA SIGMADELTA MODULATOR +5V 100nA REF IN (+) AD780 DIGITAL FILTER SYNC MCLK IN AIN6 +VIN STANDBY BUFFER CLOCK GENERATION SERIAL INTERFACE AND CONTROL LOGIC MCLK OUT REGISTER BANK AGND SCLK CS VOUT REF IN (–) GND DIN DOUT AGND DGND RDY POL RESET Figure 23. Temperature Measurement Using the AD7731 +5V AVDD 400mA REF IN (+) RL1 R1 6.
AD7731 A1 and A2 buffer the resistor string voltages and provide the AVDD and AGND voltages as well as the REF IN(+) and REF IN(–) voltages for the AD7731. The differential reference voltage for the part is +5 V. If the input voltage is from a transducer excited by the ± 5 V, the AD7731 retains its ratiometric operation with this reference voltage varying in sympathy with the analog input voltage.
AD7731 PAGE INDEX Topic Page FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 4 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 5 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DETAILED FUNCTIONAL BLOCK DIAGRAM . . .
AD7731 OUTLINE DIMENSIONS 24-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-24-1) Dimensions shown in inches and (millimeters) 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 13 1 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 12 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.430 (10.