Datasheet

AD7730/AD7730L
–39–
configured for continuous read operation when interfacing to
the 8XC51. The serial clock on the 8XC51 idles high between data
transfers and therefore the POL input of the AD7730 should be
hardwired to a logic high. The 8XC51 outputs the LSB first in a
write operation while the AD7730 expects the MSB first so the
data to be transmitted has to be rearranged before being written
to the output serial register. Similarly, the AD7730 outputs the
MSB first during a read operation while the 8XC51 expects the
LSB first. Therefore, the data read into the serial buffer needs to
be rearranged before the correct data word from the AD7730 is
available in the accumulator.
SYNC
RESET
AD7730
POL
DATA OUT
DATA IN
SCLK
CS
P3.0
P3.1
8XC51
DV
DD
Figure 21. AD7730 to 8XC51 Interface
AD7730 to ADSP-2103/ADSP-2105 Interface
Figure 22 shows an interface between the AD7730 and the
ADSP-2105 DSP processor. In the interface shown, the RDY
bit of the Status Register is again monitored to determine when
the Data Register is updated. The alternative scheme is to use
an interrupt driven system, in which case the RDY output is
connected to the IRQ2 input of the ADSP-2105. The RFS and
TFS pins of the ADSP-2105 are configured as active low out-
puts and the ADSP-2105 serial clock line, SCLK, is also config-
ured as an output. The POL pin of the AD7730 is hardwired
low. Because the SCLK from the ADSP-2105 is a continuous
clock, the CS of the AD7730 must be used to gate off the clock
once the transfer is complete. The CS for the AD7730 is active
when either the RFS or TFS outputs from the ADSP-2105 are
active. The serial clock rate on the ADSP-2105 should be lim-
ited to 3 MHz to ensure correct operation with the AD7730.
SYNC
RESET
AD7730
DATA OUT
DATA IN
SCLK
CS
DR
SCLK
ADSP-2105
DV
DD
RFS
TFS
DT
POL
Figure 22. AD7730 to ADSP-2105 Interface
REV. B