Datasheet

AD7730/AD7730L

–11–

Table III. Output Noise vs. Input Range and Update Rate (CHP = 0)

Typical Output RMS Noise in nV

Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range

Data Rate Frequency Word Normal Mode Fast Mode = 80 mV = 40 mV = 20 mV = 10 mV

150 Hz 5.85 Hz 2048 166 ms 26.6 ms 160 110 80 60

200 Hz 7.8 Hz 1536 125 ms 20 ms 190 130 95 75

300 Hz 11.7 Hz 1024 83.3 ms 13.3 ms 235 145 100 80

600 Hz 23.4 Hz 512 41.6 ms 6.6 ms 300 225 135 110

1200 Hz 46.8 Hz 256 20.8 ms 3.3 ms 435 315 210 150

Table IV. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 0)

Peak-to-Peak Resolution in Counts (Bits)

Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range

Data Rate Frequency Word Normal Mode Fast Mode = 80 mV = 40 mV = 20 mV = 10 mV

150 Hz 5.85 Hz 2048 166 ms 26.6 ms 165k (17.5) 120k (17) 80k (16.5) 55k (16)

200 Hz 7.8 Hz 1536 125 ms 20 ms 140k (17) 100k (16.5) 70k (16) 45k (15.5)

300 Hz 11.7 Hz 1024 83.3 ms 13.3 ms 115k (17) 90k (16.5) 65k (16) 40k (15.5)

600 Hz 23.4 Hz 512 41.6 ms 6.6 ms 90k (16.5) 60k (16) 50k (15.5) 30k (15)

1200 Hz 46.8 Hz 256 20.8 ms 3.3 ms 60k (16) 43k (15.5) 32k (15) 20k (14.5)

ON-CHIP REGISTERS

The AD7730 contains thirteen on-chip registers which can be accessed via the serial port of the part. These registers are summarized

in Figure 4 and in Table V and described in detail in the following sections.

COMMUNICATIONS REGISTER

STATUS REGISTER

DATA REGISTER

MODE REGISTER

FILTER REGISTER

DAC REGISTER

OFFSET REGISTER (x3)

GAIN REGISTER (x3)

TEST REGISTER

RS2 RS1 RS0

DIN

DOUT

DIN

DOUT

SELECT

DECODER

Figure 4. Register Overview

REV. B