a Bridge Transducer ADC AD7730/AD7730L The modulator output is processed by a low pass programmable digital filter, allowing adjustment of filter cutoff, output rate and settling time.
(AVDD = +5 V, DVDD = +3 V or +5 V; REF IN(+) = AVDD; REF IN(–) = AGND = DGND = CLK IN = 4.9152 MHz. All specifications TMIN to TMAX unless otherwise noted.) AD7730–SPECIFICATIONS 0 V; f Parameter B Version1 Units STATIC PERFORMANCE (CHP = 1) No Missing Codes2 Output Noise and Update Rates2 Integral Nonlinearity Offset Error2 Offset Drift vs. Temperature2 Offset Drift vs.
AD7730/AD7730L B Version1 Units ± 10 μA max 0.8 0.4 2.0 V max V max V min DVDD = +5 V DVDD = +3 V 1.4/3 1/2.5 0.8/1.4 0.4/1.1 0.4/0.8 0.4/0.8 V min to V max V min to V max V min to V max V min to V max V min to V max V min to V max DVDD = +5 V DVDD = +3 V DVDD = +5 V DVDD = +3 V DVDD = +5 V DVDD = +3 V 0.8 0.4 3.5 2.5 V max V max V min V min DVDD = +5 V DVDD = +3 V DVDD = +5 V DVDD = +3 V 0.4 V max 0.4 V max 4.0 V min VDD – 0.
AD7730/AD7730L NOTES 11 Temperature range: –40°C to +85°C. 12 Sample tested during initial release. 13 The offset (or zero) numbers with CHP = 1 are typically 3 μV precalibration. Internal zero-scale calibration reduces this by about 1 μV. Offset numbers with CHP = 0 can be up to 1 mV precalibration. Internal zero-scale calibration reduces this to 2 μV typical. System zero-scale calibration reduces offset numbers with CHP = 1 and CHP = 0 to the order of the noise.
AD7730/AD7730L Plastic DIP Package, Power Dissipation . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . 105°C/W Lead Temperature (Soldering, 10 sec) . . . . . . . +260°C TSSOP Package, Power Dissipation . . . . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . 128°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . .
AD7730/AD7730L PROGRAMMABLE GAIN AMPLIFIER BUFFER AMPLIFIER DIFFERENTIAL REFERENCE SIGMA-DELTA ADC SIGMA DELTA ADC PROGRAMMABLE DIGITAL FILTER THE BUFFER AMPLIFIER PRESENTS A HIGH IMPEDANCE INPUT STAGE FOR THE ANALOG INPUTS ALLOWING SIGNIFICANT EXTERNAL SOURCE IMPEDANCES THE PROGRAMMABLE GAIN AMPLIFIER ALLOWS FOUR UNIPOLAR AND FOUR BIPOLAR INPUT RANGES FROM +10mV TO +80mV THE REFERENCE INPUT TO THE PART IS DIFFERENTIAL AND FACILITATES RATIOMETRIC OPERATION.
AD7730/AD7730L INPUT CHOPPING SKIP MODE 22-TAP FIR FILTER IN SKIP MODE, THERE IS NO SECOND STAGE OF FILTERING ON THE PART. THE SINC3 FILTER IS THE ONLY FILTERING PERFORMED ON THE PART. IN NORMAL OPERATING MODE, THE SECOND STAGE OF THE DIGITAL FILTERING ON THE PART IS A FIXED 22-TAP FIR FILTER. IN SKIP MODE, THIS FIR FILTER IS BYPASSED. WHEN FASTSTEP™ MODE IS ENABLED AND A STEP INPUT IS DETECTED, THE SECOND STAGE FILTERING IS PERFORMED BY THE FILTER UNTIL THE OUTPUT OF THIS FILTER HAS FULLY SETTLED.
AD7730/AD7730L Pin No. Mnemonic Function 3 MCLK OUT 4 POL 5 SYNC 6 RESET 7 VBIAS When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN and MCLK OUT. If an external clock is applied to the MCLK IN, MCLK OUT provides an inverted clock signal. This clock can be used to provide a clock source for external circuits and MCLK OUT is capable of driving one CMOS load.
AD7730/AD7730L Pin No. Mnemonic Function 18 STANDBY 19 CS 20 RDY 21 DOUT 22 DIN 23 24 DVDD DGND Logic Input. Taking this pin low shuts down the analog and digital circuitry, reducing current consumption to the 5 μA range. The on-chip registers retain all their values when the part is in standby mode. Chip Select. Active low Logic Input used to select the AD7730.
AD7730/AD7730L OUTPUT NOISE AND RESOLUTION SPECIFICATION The AD7730 can be programmed to operate in either chop mode or nonchop mode. The chop mode can be enabled in ac-excited or dc-excited applications; it is optional in dc-excited applications, but chop mode must be enabled in ac-excited applications. These options are discussed in more detail in later sections.
AD7730/AD7730L Table III. Output Noise vs. Input Range and Update Rate (CHP = 0) Typical Output RMS Noise in nV Output –3 dB Data Rate Frequency SF Word Settling Time Normal Mode Settling Time Fast Mode Input Range = 80 mV Input Range = 40 mV Input Range = 20 mV Input Range = 10 mV 150 Hz 200 Hz 300 Hz 600 Hz 1200 Hz 2048 1536 1024 512 256 166 ms 125 ms 83.3 ms 41.6 ms 20.8 ms 26.6 ms 20 ms 13.3 ms 6.6 ms 3.
AD7730/AD7730L Table V. Summary of On-Chip Registers Register Name Type Size Power-On/Reset Default Value Communications Register Write Only 8 Bits Not Applicable WEN ZERO RW1 Status Register RDY STDY RW0 ZERO Read Only 8 Bits STBY NOREF MS3 RS2 RS1 RS0 CX Hex MS2 MS1 MS0 Function All operations to other registers are initiated through the Communications Register.
AD7730/AD7730L Communications Register (RS2–RS0 = 0, 0, 0) The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the Communications Register. The data written to the Communications Register determines whether the next operation is a read or write operation, the type of read operation, and to which register this operation takes place.
AD7730/AD7730L Bit Location Bit Mnemonic Description CR3 ZERO A zero must be written to this bit to ensure correct operation of the AD7730. CR2–CR0 RS2–RS0 Register Selection Bits. RS2 is the MSB of the three selection bits. The three bits select which register type the next read or write operation operates upon as shown in Table VIII. Table VIII.
AD7730/AD7730L Data Register (RS2–RS0 = 0, 0, 1); Power On/Reset Status: 000000 Hex The Data Register on the part is a read-only register which contains the most up-to-date conversion result from the AD7730. Figure 5 shows a flowchart for reading from the registers on the AD7730. The register can be programmed to be either 16 bits or 24 bits wide, determined by the status of the WL bit of the Mode Register. The RDY output and RDY bit of the Status Register are set low when the Data Register is updated.
AD7730/AD7730L MD2 MD1 MD0 Operating Mode 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Sync (Idle) Mode. In this mode, the modulator and filter are held in reset mode and the AD7730 is not processing any new samples or data. Placing the part in this mode is equivalent to exerting the SYNC input pin. However, exerting the SYNC pin does not actually force these mode bits to 0, 0, 0.
AD7730/AD7730L Bit Location Bit Mnemonic MR12 B/U Bipolar/Unipolar Bit. A 0 in this bit selects bipolar operation and the output coding is 00 . . . 000 for negative full-scale input, 10 . . . 000 for zero input, and 11 . . . 111 for positive full-scale input. A 1 in this bit selects unipolar operation and the output coding is 00 . . . 000 for zero input and 11 . . . 111 for positive full-scale input. MR11 DEN Digital Output Enable Bit.
AD7730/AD7730L Bit Location Bit Mnemonic MR2 BO Burnout Current Bit. A 1 in this bit activates the burnout currents. When active, the burnout currents connect to the selected analog input pair, one source current to the AIN(+) input and one sink current to the AIN(–) input. A 0 in this bit turns off the on-chip burnout currents. MR1–MR0 CH1–CH0 Channel Selection Bits. These bits select the analog input channel to be converted or calibrated as outlined in Table XIII.
AD7730/AD7730L Table XV. SF Ranges CHOP SKIP SF Range Output Update Rate Range (Assuming 4.9152 MHz Clock) 0 1 0 1 0 0 1 1 2048 to 150 2048 to 75 2048 to 40 2048 to 20 150 Hz to 2.048 kHz 50 Hz to 1.365 kHz 150 Hz to 7.6 kHz 50 Hz to 5.12 kHz Bit Location Bit Mnemonic FR11–FR10 FR9 ZERO SKIP FR8 FAST FR7–FR6 FR5 ZERO AC FR4 CHP FR3–FR0 DL3–DL0 REV. B Description A zero must be written to these bits to ensure correct operation of the AD7730. FIR Filter Skip Bit.
AD7730/AD7730L DAC Register (RS2–RS0 = 1, 0, 0); Power On/Reset Status: 20 Hex The DAC Register is an 8-bit register from which data can either be read or to which data can be written. This register provides the code for the offset-compensation DAC on the part. Table XVI outlines the bit designations for the DAC Register. DR0 through DR7 indicate the bit location, DR denoting the bits are in the DAC Register. DR7 denotes the first bit of the data stream.
AD7730/AD7730L READING FROM AND WRITING TO THE ON-CHIP REGISTERS The AD7730 contains a total of thirteen on-chip registers. These registers are all accessed over a three-wire interface. As a result, addressing of registers is via a write operation to the topmost register on the part, the Communications Register. Figure 5 shows a flowchart for reading from the different registers on the part summarizing the sequence and the words to be written to access each of the registers.
AD7730/AD7730L CALIBRATION OPERATION SUMMARY The AD7730 contains a number of calibration options as outlined previously. Table XVII summarizes the calibration types, the operations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to monitor the hardware RDY pin using either interrupt-driven or polling routines. The second method is to do a software poll of the RDY bit in the Status Register.
AD7730/AD7730L CIRCUIT DESCRIPTION The AD7730 is a sigma-delta A/D converter with on-chip digital filtering, intended for the measurement of wide dynamic range, low-frequency signals such as those in weigh-scale, strain-gage, pressure transducer or temperature measurement applications. It contains a sigma-delta (or charge-balancing) ADC, a calibration microcontroller with on-chip static RAM, a clock oscillator, a digital filter and a bidirectional serial communications port.
AD7730/AD7730L ANALOG INPUT Analog Input Channels Offset DAC The purpose of the Offset DAC is to either add or subtract an offset so the input range at the input to the PGA is as close as possible to the nominal. If the output of the 6-bit Offset DAC is 0 V, the differential voltage ranges that appear at the analog input to the part will also appear at the input to the PGA.
AD7730/AD7730L Burnout Currents The AD7730 contains two 100 nA constant current generators, one source current from AVDD to AIN(+) and one sink current from AIN(–) to AGND. The currents are switched to the selected analog input pair. Both currents are either on or off, depending on the BO bit of the Mode Register. These currents can be used in checking that a transducer is still operational before attempting to take measurements on that channel.
AD7730/AD7730L SIGMA-DELTA MODULATOR A sigma-delta ADC generally consists of two main blocks, an analog modulator and a digital filter. In the case of the AD7730, the analog modulator consists of a difference amplifier, an integrator block, a comparator and a feedback DAC as illustrated in Figure 9. In operation, the analog signal sample is fed to the difference amplifier along with the output of the feedback DAC. The difference between these two signals is integrated and fed to the comparator.
AD7730/AD7730L Chop Mode With chop mode enabled on the AD7730, the signal processing chain is synchronously chopped at the analog input and at the output of the first stage filter. This means that for each output of the first stage filter to be computed, the full settling time of the filter has to elapse. This results in an output rate from the filter that is three times lower than for a given SF word than for nonchop mode.
AD7730/AD7730L Figure 13 shows the frequency response for the AD7730 with the second stage filter set for normal FIR operation, chop mode disabled, the decimal equivalent of the word in the SF bits set to 1536 and a master clock frequency of 4.9152 MHz. The response is analogous to that of Figure 11, with the three-times-larger SF word producing the same 200 Hz output rate. Once again, the response will scale proportionally with master clock frequency. The response is shown from dc to 100 Hz.
AD7730/AD7730L FASTStep Mode The second mode of operation of the second stage filter is in FASTStep mode which enables it to respond rapidly to step inputs. This FASTStep mode is enabled by placing a 1 in the FAST bit of the Filter Register. If the FAST bit is 0, the part continues to process step inputs with the normal FIR filter as the second stage filter. With FASTStep mode enabled, the second stage filter will continue to process steady state inputs with the filter in its normal FIR mode of operation.
AD7730/AD7730L Internally in the AD7730, the coefficients are normalized before being used to scale the words coming out of the digital filter. The offset calibration register contains a value which, when normalized, is subtracted from all conversion results. The gain calibration register contains a value which, when normalized, is multiplied by all conversion results. The offset calibration coefficient is subtracted from the result prior to the multiplication by the gain coefficient.
AD7730/AD7730L user must write either 0, 0, 1 or 0, 1, 0 to the MD2, MD1, MD0 bits of the Mode Register to initiate a conversion. If RDY is low before (or goes low during) the calibration command write to the Mode Register, it may take up to one modulator cycle (MCLK IN/32) before RDY goes high to indicate that calibration is in progress. Therefore, RDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the Mode Register.
AD7730/AD7730L The range of input span in both the unipolar and bipolar modes has a minimum value of 0.8 × FS and a maximum value of 2.1 × FS. However, the span (which is the difference between the bottom of the AD7730’s input range and the top of its input range) has to take into account the limitation on the positive full-scale voltage. The amount of offset which can be accommodated depends on whether the unipolar or bipolar mode is being used.
AD7730/AD7730L Reset Input MCLK IN C1 CRYSTAL OR CERAMIC RESONATOR C2 The RESET input on the AD7730 resets all the logic, the digital filter and the analog modulator while all on-chip registers are reset to their default state. RDY is driven high and the AD7730 ignores all communications to any of its registers while the RESET input is low.
AD7730/AD7730L POWER SUPPLIES There is no specific power sequence required for the AD7730, either the AVDD or the DVDD supply can come up first. While the latch-up performance of the AD7730 is very good, it is important that power is applied to the AD7730 before signals at REF IN, AIN or the logic input pins in order to avoid latch-up caused by excessive current.
AD7730/AD7730L SERIAL INTERFACE The AD7730’s programmable functions are controlled via a set of on-chip registers. Access to these registers is via the part’s serial interface. After power-on or RESET, the device expects a write to its Communications Register. The data written to this register determines whether the next operation to the part is a read or a write operation and also determines to which register this read or write operation occurs.
AD7730/AD7730L In DSP applications, the SCLK is generally a continuous clock. In these applications, the CS input for the AD7730 is generated from a frame synchronization signal from the DSP. In these applications, the first edge after CS goes low is the active edge. The MSB of the data to be shifted into the DSP must be set up prior to this first active edge. Unlike microcontroller applications, the DSP does not provide a clock edge to clock the MSB from the AD7730.
AD7730/AD7730L CONFIGURING THE AD7730 The AD7730 contains twelve on-chip registers that can be accessed via the serial interface. Figure 5 and Figure 6 have outlined a flowchart for the reading and writing of these registers. Table XIX and Table XX outline sample pseudo-code for some commonly used routines. The required operating conditions will dictate the values loaded to the Mode, Filter and DAC Registers. The values given here are for example purposes only. Table XIX.
AD7730/AD7730L MICROCOMPUTER/MICROPROCESSOR INTERFACING The AD7730’s flexible serial interface allows for easy interface to most microcomputers and microprocessors. The pseudo-code of Table XIX and Table XX outline typical sequences for interfacing a microcontroller or microprocessor to the AD7730. Figures 20, 21 and 22 show some typical interface circuits. The serial interface on the AD7730 has the capability of operating from just three wires and is compatible with SPI interface protocols.
AD7730/AD7730L configured for continuous read operation when interfacing to the 8XC51. The serial clock on the 8XC51 idles high between data transfers and therefore the POL input of the AD7730 should be hardwired to a logic high. The 8XC51 outputs the LSB first in a write operation while the AD7730 expects the MSB first so the data to be transmitted has to be rearranged before being written to the output serial register.
AD7730/AD7730L can be used with the excitation voltage and analog ground connected local to the AD7730’s REF IN(+) and REF IN(–) terminals. Illustrating a major advantage of the AD7730, the 5 V excitation voltage for the bridge can be used directly as the reference voltage for the AD7730, eliminating the need for precision matched resistors in generating a scaled-down reference. APPLICATIONS The on-chip PGA allows the AD7730 to handle analog input voltage ranges as low as 10 mV full scale.
AD7730/AD7730L discrete matched bipolar or MOS transistors, or a dedicated bridge driver chip such as the 4427 from Micrel can be used to perform the task. Long lead lengths from the bridge to the AD7730 facilitate the pickup of mains frequency on the analog input, the reference input and the power supply. The analog inputs to the AD7730 are buffered, which allows the user to connect whatever noise reduction capacitors are necessary in the application.
AD7730/AD7730L a minimum of 1.2 V. The 10 V excitation voltage must be reduced to 5 V before being applied as the reference voltage for the AD7730. Bipolar Excitation of the Bridge As mentioned previously, some applications will require that the AD7730 handle inputs from a bridge that is excited by a bipolar voltage. The number of applications requiring this are limited, but with the addition of some external components the AD7730 is capable of handling such signals.
APPENDIX A AD7730L SPECIFICATIONS –43–
a APPENDIX–AD7730L* GENERAL DESCRIPTION LOW POWER BRIDGE TRANSDUCER ADC The AD7730L is a complete low power analog front-end for weigh-scale and pressure measurement applications. The device accepts low level signals directly from a transducer and outputs a serial digital word. The input signal is applied to a proprietary programmable gain front end based around an analog modulator.
AD7730/AD7730L (AV = +5 V, DV = +3 V or +5 V; REF IN(+) = AD7730L–SPECIFICATIONS AV ; REF IN(–) = AGND = DGND = 0 V; f = 2.4576 MHz. All specifications T to T unless otherwise noted.) DD DD DD CLK IN MIN 1 Parameter B Version STATIC PERFORMANCE (CHP = 1) No Missing Codes2 Output Noise and Update Rates 2 Integral Nonlinearity Offset Error2 Offset Drift vs. Temperature2 Offset Drift vs.
AD7730/AD7730L Parameter LOGIC INPUTS Input Current All Inputs Except SCLK and MCLK IN VINL, Input Low Voltage VINL, Input Low Voltage VINH, Input High Voltage SCLK Only (Schmitt Trigerred Input) VT+ VT+ VT– VT– VT+ – VT– VT+ – VT– MCLK IN Only VINL, Input Low Voltage VINL, Input Low Voltage VINH, Input High Voltage VINH, Input High Voltage B Version1 Units ± 10 μA max 0.8 0.4 2.0 V max V max V min DVDD = +5 V DVDD = +3 V 1.4/3 1/2.5 0.8/1.4 0.4/1.1 0.4/0.8 0.4/0.
AD7730/AD7730L NOTES 11 Temperature range: –40°C to +85°C. 12 Sample tested during initial release. 13 The offset (or zero) numbers with CHP = 1 are typically 3 μV precalibration. Internal zero-scale calibration reduces this by about 1 μV. Offset numbers with CHP = 0 can be up to 1 mV precalibration. Internal zero-scale calibration reduces this to 2 μV typical. System zero-scale calibration reduces offset numbers with CHP = 1 and CHP = 0 to the order of the noise.
AD7730/AD7730L OUTPUT NOISE AND RESOLUTION SPECIFICATION The AD7730L can be programmed to operate in either chop mode or nonchop mode. The chop mode can be enabled in ac-excited or dc-excited applications; it is optional in dc-excited applications, but chop mode must be enabled in ac-excited applications. These options are discussed in more detail in earlier sections.
AD7730/AD7730L Table XXIII. Output Noise vs. Input Range and Update Rate (CHP = 0) Typical Output RMS Noise in nV Output –3 dB Data Rate Frequency SF Word Settling Time Normal Mode Settling Time Fast Mode Input Range = 80 mV Input Range = 40 mV Input Range = 20 mV Input Range = 10 mV 75 Hz 100 Hz 150 Hz 300 Hz 600 Hz 2048 1536 1024 512 256 332 ms 250 ms 166 ms 83 ms 41.6 ms 53.2 ms 40 ms 26.6 ms 13.3 ms 6.
AD7730/AD7730L PAGE INDEX Topic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 AD7730 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . 2 TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 4 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 5 ORDERING GUIDE . . . . . . . . . . . . .
AD7730/AD7730L OUTLINE DIMENSIONS 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 24 13 1 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 12 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX 0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.
AD7730/AD7730L 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 0.
AD7730/AD7730L REVISION HISTORY 6/12—Rev. A to Rev. B Changed Differential Linearity from −0.25/0.75 LSB to ±0.75 LSB ..........................................................................................46 Changes to Ordering Guide ...........................................................52 1/98—Rev. 0 to Rev. A ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01189-0-6/12(B) REV.
