Datasheet

AD7723
Rev. C | Page 6 of 32
TIMING SPECIFICATIONS
AV
DD
= DV
DD
= 5 V ± 5%; AGND = AGND1 = DGND = 0 V; f
CLKIN
= 19.2 MHz; C
L
= 50 pF; SFMT = logic low or high, CFMT = logic low
or high; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit
CLKIN Frequency f
CLK
1 19.2 MHz
CLKIN Period (t
CLK
– 1/f
CLK
) t
1
0.052 1 µs
CLKIN Low Pulse Width t
2
0.45 × t
1
0.55 × t
1
CLKIN High Pulse Width t
3
0.45 × t
1
0.55 × t
1
CLKIN Rise Time t
4
5 ns
CLKIN Fall Time t
5
5 ns
FSI Setup Time t
6
0 5 ns
FSI Hold Time t
7
0 5 ns
FSI High Time
1
t
8
1 t
CLK
CLKIN to SCO Delay t
9
25 40 ns
SCO Period
2
, SCR = 1 t
10
2 t
CLK
SCO Period
2
, SCR = 0 t
10
1 t
CLK
SCO Transition to FSO High Delay t
11
0 5 ns
SCO Transition to FSO Low Delay t
12
0 5 ns
SCO Transition to SDO Valid Delay t
13
5 12 ns
SCO Transition from FSI
3
t
14
60 t
CLK
+ t
2
SDO Enable Delay Time t
15
5 20 ns
SDO Disable Delay Time t
16
5 20 ns
DRDY
High Time
2
t
17
2 t
CLK
Conversion Time
2
(Refer to Table 3 and Table 4) t
18
16/32 t
CLK
CLKIN to
DRDY
Transition
t
19
35 50 ns
CLKIN to DATA Valid t
20
20 35 ns
CS
/
RD
Setup Time to CLKIN
t
21
0 ns
CS
/
RD
Hold Time to CLKIN
t
22
20 ns
Data Access Time t
23
20 35 ns
Bus Relinquish Time t
24
20 35 ns
SYNC Input Pulse Width t
25
1 t
CLK
SYNC Low Time before CLKIN Rising t
26
0 ns
DRDY
High Delay after Rising SYNC
t
27
25 35 ns
DRDY
Low Delay after SYNC Low
t
28
2049 t
CLK
1
FSO pulses are gated by the release of FSI (going low).
2
Guaranteed by design.
3
Frame sync is initiated on the falling edge of CLKIN.
I
OL
1.6mA
1.6V
C
L
50pF
TO
OUTPUT
PIN
I
OH
200µA
01186-002
Figure 2. Load Circuit for Timing Specifications