Datasheet

AD7723
Rev. C | Page 26 of 32
The master device is selected by setting TSI to a logic low and
connecting its FSO to DOE. The slave device is selected with its
TSI pin tied high and both its FSI and DOE controlled from the
master’s FSO. Since the FSO of the master controls the DOE
input of both the master and slave, one ADC’s SDO is active
while the other is high impedance (Figure 46). When the master
transmits its conversion result during the first 16 SCO cycles of
a data transmission frame, the low level on DOE sets the slave’s
SDO high impedance. Once the master completes transmitting
its conversion data, its FSO goes high and triggers the slave’s FSI
to begin its data transmission frame.
Since FSO pulses are gated by the release of FSI (going low) and
the FSI of the slave device is held high during its data
transmission, the FSO from the master device must be used for
connection to the host processor.
CLKIN
FSI
SCO
FSO (MASTER)
FSI (SLAVE)
DOE (MASTER AND SLAVE)
SDO (MASTER)
SDO (SLAVE)
D1 D0 D15 D14
D15 D14 D1 D0
t
11
t
12
t
13
t
9
t
15
t
16
t
16
t
15
01186-046
Figure 46. Serial Mode 1 Timing for Two-Channel Multiplexed Operation