Datasheet

AD7723
Rev. C | Page 24 of 32
DATA INTERFACING
The AD7723 offers a choice of serial or parallel data interface
options to meet the requirements of a variety of system
configurations. In parallel mode, multiple AD7723s can easily
be configured to share a common data bus. Serial mode is ideal
when it is required to minimize the number of data interface
lines connected to a host processor. In either case, careful
attention to the system configuration is required to realize the
high dynamic range available with the AD7723. Consult the
recommendations in the Grounding and Layout section. The
following recommendations for parallel interfacing also apply
for the system design when using the serial mode.
PARALLEL INTERFACE
When using the AD7723, place a buffer/latch adjacent to the
converter to isolate the converter’s data lines from any noise
that may be on the data bus. Even though the AD7723 has three
state outputs, use of an isolation latch represents good design
practice.
Figure 44 shows how the parallel interface of the AD7723 can
be configured to interface with the system data bus of a
microprocessor or a microcontroller, such as the MC68HC16 or
8XC251. With
CS
and
RD
tied permanently low, the data output
bits are always active. When
DRDY
goes high for two clock
cycles, the rising edge of
DRDY
is used to latch the conversion
data before a new conversion result is loaded into the output
data register. The falling edge of
DRDY
then sends an
appropriate interrupt signal for interface control. Alternatively,
if buffers are used instead of latches, the falling edge of
DRDY
provides the necessary interrupt when a new output word is
available from the AD7723.
DSP
ADDR
DECODE
DB15
DRDY
CS
RD
16 16
OE
D15
RD
INTERRUPT
ADDR
AD7723
74XX16374
01186-044
Figure 44. Parallel Interface Connection