Datasheet

REV. B
AD7722
–7–
t
15
t
16
DOE
SDO
Figure 5. Serial Mode Timing for Data Output Enable and Serial Data Output (TSI = Logic Low)
t
17
t
20
t
21
t
23
RD
DB0–DB15
t
22
VALID DATA
t
25
t
24
t
18
t
19
CS
DRDY
Figure 6. Parallel Mode Read Timing
CLKIN
t
29
t
30
t
31
t
27
t
26
t
28
MAX
t
28
MIN
SYNC, RESET
DVAL
DRDY
Figure 7. SYNC and RESET Timing, Serial and Parallel Mode
CLKIN
SYNC, RESET
DVAL
DRDY
8192 t
CLK
8192 t
CLK
8192 t
CLK
8192 t
CLK
512 t
CLK
512 t
CLK
512 t
CLK
t
38
t
34
t
37
UNI = 1
t
37
UNI = 0
t
35
t
36
Figure 8. Calibration Timing, Serial and Parallel Mode