Datasheet

AD7721
REV. A
–4–
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
, T
MAX
Parameter (A, S Versions) Units Conditions/Comments
Serial Interface
f
CLK
3
100 kHz min Master Clock Frequency
15 MHz max 15 MHz for Specified Performance
t
CLK LO
0.45 × t
CLK
ns min Master Clock Input Low Time
t
CLK HI
0.45 × t
CLK
ns min Master Clock Input High Time
t
1
t
CLK
ns nom DRDY High Time
t
2
4
t
CLK HI
– 10 ns min RFS Low to SCLK Falling Edge Setup Time
t
3
20 ns max RFS Low to Data Valid Delay
t
4
t
CLK HI
ns nom SCLK High Pulse Width
t
5
t
CLK LO
ns nom SCLK Low Pulse Width
t
6
25 ns max SCLK Rising Edge to Data Valid Delay
t
7
0 ns min RFS to SCLK Falling Edge Hold Time
t
8
5
0 ns min Bus Relinquish Time after Rising Edge of RFS
20 ns max
t
9
32 × t
CLK
ns nom Period between Consecutive DRDY Rising Edges
Parallel Interface
f
CLK
3
100 kHz min Master Clock Frequency
10 MHz max 10 MHz for Specified Performance
t
CLK LO
0.45 × t
CLK
ns min Master Clock Input Low Time
t
CLK HI
0.45 × t
CLK
ns min Master Clock Input High Time
Read Operation
t
10
2 × t
CLK
ns nom DRDY High Time
t
11
30 ns max Data Access Time after Falling Edge of DRDY
t
12
32 × t
CLK
ns nom Period between Consecutive DRDY Rising Edges
Write Operation
t
13
35 ns min WR Pulse Width
t
14
20 ns min Data Valid to WR High Setup Time
t
15
0 ns min Data Valid to WR High Hold Time
NOTES
The timing is measured with a load of 50 pF on SCLK and DRDY. SCLK can be operated with a load capacitance of 50 pF maximum.
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
All digital outputs are timed with the load circuit below and, except for t
2
, are defined as the time required for an output to cross 0.8 V or 2 V, whichever occurs last.
3
The AD7721 is production tested with f
CLK
at 10 MHz for parallel mode operation and at 15 MHz for serial mode operation. However, it is guaranteed by character-
ization to operate with CLK frequencies down to 100 kHz.
4
t
2
is the time from RFS crossing 1.6 V to SCLK crossing 0.8 V.
5
t
8
and t
15
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown below. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics is the true bus
relinquish time of the part and, as such, is independent of external bus loading capacitance.
TO
OUTPUT
PIN
+1.6V
I
OH
I
OL
C
L
50pF
1.6mA
200mA
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
(AV
DD
= +5 V 6 5%; DV
DD
= +5 V 6 5%; AGND = DGND = 0 V, REFIN= +2.5 V
unless otherwise noted)