Datasheet

REV. A
AD7719
–16–
FILTER REGISTER
DOUT
DIN
TEST REGISTER
DOUT
DIN
ID REGISTER
DOUT
AUX ADC GAIN REGISTER
DOUT
DIN
ADC STATUS REGISTER
DOUT
MODE REGISTER
DOUT
DIN
MAIN ADC CONTROL REGISTER
DOUT
DIN
AUX ADC CONTROL REGISTER
DOUT
DIN
I/O CONTROL REGISTER
DOUT
DIN
MAIN ADC GAIN REGISTER
DOUT
DIN
AUX ADC OFFSET REGISTER
DOUT
DIN
MAIN ADC OFFSET REGISTER
DOUT
DIN
AUX ADC DATA REGISTER
DOUT
MAIN ADC DATA REGISTER
DOUT
WEN R/W 00 A1A2A3 A0
COMMUNICATIONS REGISTER
DOUT
DIN
REGISTER
SELECT
DECODER
Figure 10. On-Chip Registers
ON-CHIP REGISTERS
Both the main and auxiliary ADC channels are controlled and con-
figured via a number of on-chip registers as shown in Figure 10 and
described in more detail in the following pages. In the following
descriptions, SET implies a logic 1 state and CLEARED implies
a logic 0 state, unless otherwise stated.