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AD7719

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REV. A

Low Voltage, Low Power,

Factory-Calibrated 16-/24-Bit Dual - ADC

FEATURES

HIGH RESOLUTION - ADCs

2 Independent ADCs (16- and 24-Bit Resolution)

Factory-Calibrated (Field Calibration Not Required)

Output Settles in 1 Conversion Cycle (Single

Conversion Mode)

Programmable Gain Front End

Simultaneous Sampling and Conversion of 2

Signal Sources

Separate Reference Inputs for Each Channel

Simultaneous 50 Hz and 60 Hz Rejection at 20 Hz

Update Rate

ISOURCE Select

™

24-Bit No Missing Codes—Main ADC

13-Bit p-p Resolution @ 20 Hz, 20 mV Range

18-Bit p-p Resolution @ 20 Hz, 2.56 V Range

INTERFACE

3-Wire Serial

SPI

, QSPI™, MICROWIRE™, and DSP Compatible

Schmitt Trigger on SCLK

POWER

Specified for Single 3 V and 5 V Operation

Normal: 1.5 mA Typ @ 3 V

Power-Down: 10 A (32 kHz Crystal Running)

ON-CHIP FUNCTIONS

Rail-Rail Input Buffer and PGA

4-Bit Digital I/O Port

On-Chip Temperature Sensor

Dual Switchable Excitation Current Sources

Low-Side Power Switches

Reference Detect Circuit

APPLICATIONS

Sensor Measurement

Temperature Measurement

Pressure Measurement

Weigh Scales

Portable Instrumentation

4 to 20 mA Transmitters

GENERAL DESCRIPTION

The AD7719 is a complete analog front end for low frequency

measurement applications. It contains two high resolution Σ-∆

ADCs, switchable matched excitation current sources, low-side

power switches, digital I/O port, and temperature sensor. The

24-bit main channel with PGA accepts fully differential, unipolar,

and bipolar input signal ranges from 1.024 × REFIN1/128 to

1.024 × REFIN1. Signals can be converted directly from a trans-

ducer without the need for signal conditioning. The 16-bit auxiliary

channel has an input signal range of REFIN2 or REFIN2/2.

The device operates from a 32 kHz crystal with an on-chip

PLL generating the required internal operating frequency. The

output data rate from the part is software programmable. The

peak-to-peak resolution from the part varies with the programmed

gain and output data rate.

The part operates from a single 3 V or 5 V supply. When oper-

ating from 3 V supplies, the power dissipation for the part is

4.5 mW with both ADCs enabled and 2.85 mW with only the

main ADC enabled in unbuffered mode. The AD7719 is housed

in 28-lead SOIC and TSSOP packages.

FUNCTIONAL BLOCK DIAGRAM

MUX

IEXC1

200A

IEXC2

200A

AGND

BUF

PGA

MUX1

TEMP

SENSOR

I/O PORT

MAIN CHANNEL

24-BIT - ADC

AUXILIARY CHANNEL

16-BIT - ADC

REFERENCE

DETECT

OSC. AND

PLL

SERIAL

INTERFACE

AND

CONTROL

LOGIC

DGND

IOUT1

IOUT2

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AGND REFIN2 PWRGND P1/SW1 P2/SW2 P3 P4

DOUT

DIN

SCLK

RDY

RESET

XTAL1 XTAL2REFIN1(+) REFIN1(–)

AD7719

MUX2

Summary of content (40 pages)

PAGE 1
a Low Voltage, Low Power, Factory-Calibrated 16-/24-Bit Dual - ADC AD7719 FEATURES HIGH RESOLUTION - ADCs 2 Independent ADCs (16- and 24-Bit Resolution) Factory-Calibrated (Field Calibration Not Required) Output Settles in 1 Conversion Cycle (Single Conversion Mode) Programmable Gain Front End Simultaneous Sampling and Conversion of 2 Signal Sources Separate Reference Inputs for Each Channel Simultaneous 50 Hz and 60 Hz Rejection at 20 Hz Update Rate APPLICATIONS Sensor Measurement Temperature Measur
PAGE 2
AD7719 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 7 DIGITAL INTERFACE . . . . . . . . . . . . . .
PAGE 3
AD7719–SPECIFICATIONS1(AV DD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications TMIN to TMAX, unless otherwise noted.) Parameter ADC CHANNEL SPECIFICATION Output Update Rate MAIN CHANNEL No Missing Codes2 Resolution Output Noise and Update Rates Integral Nonlinearity Offset Error3 Offset Error Drift vs. Temperature 4 Full-Scale Error5, 6, 7 Gain Drift vs.
PAGE 4
AD7719 Parameter AD7719B Unit Test Conditions AUXILIARY CHANNEL (continued) Offset Error3 Offset Error Drift vs. Temperature 4 Full-Scale Error6, 7 Gain Drift vs. Temperature4 Negative Full-Scale Error Power Supply Rejection (PSR) ±3 ±10 ±0.75 0.
PAGE 5
AD7719 Parameter LOGIC INPUTS All Inputs Except SCLK and XTAL1 2 VINL, Input Low Voltage VINH, Input High Voltage SCLK Only (Schmitt-Triggered Input) 2 VT(+) VT(–) VT(+) – VT(–) VT(+) VT(–) VT(+) – VT(–) XTAL1 Only2 VINL, Input Low Voltage VINH, Input High Voltage VINL, Input Low Voltage VINH, Input High Voltage Input Currents Input Capacitance2 LOGIC OUTPUTS (Excluding XTAL2) VOH, Output High Voltage2 VOL, Output Low Voltage2 VOH, Output High Voltage2 VOL, Output Low Voltage 2 Floating-State Leakage Curren
PAGE 6
AD7719 Parameter AD7719B Unit Test Conditions 1.1 mA max 0.55 mA max AIDD Current (Aux ADC) AIDD Current (Main and Aux ADC) 0.3 1.25 mA max mA max DIDD (ADC Disable Mode)13 0.35 0.4 0.15 10 2 30 8 1 mA max mA max mA max µA max µA max µA max µA max µA max AVDD = 3 V or 5 V, Buffered Mode, 0.85 mA typ AVDD = 3 V or 5 V, Unbuffered Mode, 0.45 mA typ AVDD = 3 V or 5 V, 0.25 mA typ AVDD = 3 V or 5 V, Main ADC Buffered, 1 mA typ DVDD = 3 V, 0.25 mA typ DVDD = 5 V, 0.
PAGE 7
AD7719 TIMING CHARACTERISTICS1, 2 (AV DD = 2.7 V to 3.6 V or AVDD = 4.75 V to 5.25 V; DVDD = 2.7 V to 3.6 V or DVDD = 4.75 V to 5.25 V; AGND = DGND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted.) Parameter t1 t2 Read Operation t3 t4 t5 4 t5A4, 5 t6 t7 t8 t9 6 t10 Write Operation t11 t12 t13 t14 t15 t16 Limit at TMIN, TMAX (B Version) Unit Conditions/Comments 32.
PAGE 8
AD7719 of the output register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. CS is used to select the device. It can be used to decode the AD7719 in systems where a number of parts are connected to the serial bus. DIGITAL INTERFACE As previously outlined, the AD7719’s programmable functions are controlled using a set of on-chip registers.
PAGE 9
AD7719 The serial interface can be reset by exercising the RESET input on the part. It can also be reset by writing a series of 1s on the DIN input. If a logic 1 is written to the AD7719 DIN line for at least 32 serial clock cycles, the serial interface is reset. This ensures that in 3-wire systems, if the interface gets lost, either via a software error or by some glitch in the system, it can be reset back to a known state.
PAGE 10
AD7719 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Mnemonic Function 16 P2/SW2 17 18 PWRGND P1/SW1 19 RESET 20 SCLK 21 CS 22 RDY 23 DOUT 24 DIN 25 26 27 28 DGND DVDD XTAL2 XTAL1 Dual-Purpose Pin. It can act as a general-purpose output (P2) bit referenced between AVDD and AGND or as a low-side power switch (SW2) to PWRGND. Ground Point for the Low-Side Power Switches SW2 and SW1. PWRGND must be tied to AGND. Dual-Purpose Pin.
PAGE 11
Typical Performance Characteristics– AD7719 26 8389600 8389400 24 NO MISSING CODES (Min) CODE READ 8389200 8389000 8388800 8388600 8388400 22 20 18 8388200 8388000 16 0 100 200 300 400 500 600 READING NO. 700 800 900 1000 0 10 20 30 40 50 60 70 80 90 100 110 UPDATE RATE (Hz) MAIN ADC IN BUFFERED MODE RMS NOISE = 0.58 V rms TA = 25 C VREF = 2.5V AVDD = DVDD = 5V INPUT RANGE = 20mV REFIN1(+)–REFIN1(–) = 2.5V UPDATE RATE = 19.79Hz TPC 4. No-Missing-Codes Performance TPC 1.
PAGE 12
AD7719 AVDD = DVDD = 5V TA = 25 C VDD OSCILLATOR TIME BASE = 100ms/DIV TRACE 1 = TRACE 2 = 2V/DIV TPC 7. Typical Oscillator Power-Up DUAL-CHANNEL ADC CIRCUIT INFORMATION Overview The AD7719 incorporates two independent Σ-∆ ADC channels (main and auxiliary) with on-chip digital filtering intended for the measurement of wide dynamic range, low frequency signals such as those in weigh-scale, strain gage, pressure transducer, or temperature measurement applications.
PAGE 13
AD7719 fCHOP ANALOG INPUT fMOD fCHOP fADC - MUX 3 (8 1 SF ) XOR MOD1 3 (8 SF ) 1 2 DIGITAL OUTPUT SINC3 FILTER AIN + VOS AIN – VOS Figure 5. Auxiliary ADC Channel Block Diagram Both Channels The operation of the aux channel is identical to the main channel with the exception that there is no PGA on the aux channel. The input chopping is incorporated into the input multiplexer while the output chopping is accomplished by an XOR gate at the output of the modulator.
PAGE 14
AD7719 0 0 –20 –20 –40 –40 ATTENUATION (dB) ATTENUATION (dB) –60 –80 –100 –120 –140 –60 –80 –100 –120 –160 –140 –180 –200 0 –160 50 100 150 200 250 300 350 400 450 500 550 600 650 700 0 10 20 30 FREQUENCY (Hz) 50 60 70 80 90 100 SF = 69 OUTPUT DATA RATE = 19.8Hz INPUT BANDWIDTH = 4.74Hz FIRST NOTCH = 9.9Hz 50Hz REJECTION = –66dB, 50Hz 1Hz REJECTION = –60dB 60Hz REJECTION = –117dB, 60Hz 1Hz REJECTION = –94dB SF = 13 OUTPUT DATA RATE = 105Hz INPUT BANDWIDTH = 25.
PAGE 15
AD7719 Table II. Typical Output RMS Noise vs. Input Range and Update Rate for Main ADC (Buffered Mode) Output RMS Noise in V SF Word Data Update Rate (Hz) 20 mV 40 mV 80 mV Input Range 160 mV 320 mV 640 mV 1.28 V 2.56 V 13 69 255 105.3 19.79 5.35 1.50 0.65 0.35 1.60 0.65 0.37 1.75 0.65 0.37 4.50 0.95 0.51 6.70 1.40 0.82 11.75 2.30 1.25 1.50 0.60 0.35 3.50 0.65 0.37 Table III. Peak-to-Peak Resolution vs.
PAGE 16
AD7719 ON-CHIP REGISTERS Both the main and auxiliary ADC channels are controlled and configured via a number of on-chip registers as shown in Figure 10 and described in more detail in the following pages. In the following descriptions, SET implies a logic 1 state and CLEARED implies a logic 0 state, unless otherwise stated.
PAGE 17
AD7719 Table VIII. Registers—Quick Reference Guide Register Name Type Size Power-On/Reset Default Value Communications Write Only 8 Bits Not Applicable MSB WEN LSB R/W 0 Status Register 0 Read Only A3 A2 8 Bits A1 A0 0x00 MSB RDY0 LSB RDY1 CAL Mode Register NOREF Read/Write ERR0 ERR1 8 Bits 0 0x00 LSB BUF 0 CHCON OSCPD MD2 All operations to other registers are initiated through the Communications register.
PAGE 18
AD7719 Register Name Power-On/Reset Default Value Type Size Function Read Only 16 Bits or 24 Bits 0x00 0000 Provides the most up-to-date conversion result from the main ADC. Main ADC data register length can be programmed to be 16-bit or 24-bit. Read Only 16 Bits 0x0000 Provides the most up-to-date conversion result from the auxiliary ADC. Aux ADC data register length is 16 bits. Read/Write 24 Bits 0x80 0000 Contains a 24-bit word that is the offset calibration coefficient for the part.
PAGE 19
AD7719 register. This is the default state of the interface, and on power-up or after a RESET, the AD7719 is in this default state waiting for a write operation to the Communications register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the AD7719 to this default state by resetting the part. Table IX outlines the bit designations for the Communications register.
PAGE 20
AD7719 Status Register (A3, A2, A1, A0 = 0, 0, 0, 0; Power-On Reset = 0x00) The ADC Status register is an 8-bit read-only register. To access the ADC Status register, the user must write to the Communications register selecting the next operation to be a read and loading bits A3 to A0 with 0, 0, 0, 0. Table XI outlines the bit designations for the Status register. SR0 through SR7 indicate the bit location, with SR denoting that the bits are in the Status register.
PAGE 21
AD7719 Mode Register (A3, A2, A1, A0 = 0, 0, 0, 1; Power-On Reset = 0x00) The Mode register is an 8-bit register from which data can be read or to which data can be written. This register configures the operating modes of the AD7719. Table XII outlines the bit MR7 MR6 MR5 0 (0) BUF (0) 0 (0) designations for the Mode register. MR7 through MR0 indicate the bit location, with MR denoting the bits are in the Mode register. MR7 denotes the first bit of the data stream.
PAGE 22
AD7719 calibration commences. On completion, the appropriate calibration registers are written, the relevant bits in STATUS are written, and the MD2–0 bits are reset to 001 to indicate the ADC is back in Idle mode. Operating Characteristics when Addressing the Mode and Control Registers 1. Any change to the MD bits will immediately reset both ADCs. A write to the MD2–0 bits with no change is also treated as a reset. (See exception to this in Note 3.) 2.
PAGE 23
AD7719 Table XIII. Main ADC Control Register (AD0CON) Bit Designations (continued) Bit Location Bit Name Description AD0CON2 AD0CON1 RN2 RN1 Main ADC Range Bits. Written by the user to select the main ADC input range as follows. AD0CON0 RN0 RN2 0 0 0 0 1 1 1 1 RN1 0 0 1 1 0 0 1 1 RN0 0 1 0 1 0 1 0 1 Selected Main ADC Input Range (VREF = 2.5 V) ±20 mV ±40 mV ±80 mV ±160 mV ±320 mV ±640 mV ±1.28 V ±2.56 V for the aux ADC control register.
PAGE 24
AD7719 FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0 SF7 (0) SF6 (1) SF5 (0) SF4 (0) SF3 (0) SF2 (1) SF1 (0) SF0 (1) Filter Register (A3, A2, A1, A0 = 0, 1, 0, 0; Power-On Reset = 0x45) The Filter register is an 8-bit register from which data can be read or to which data can be written. This register determines the amount of averaging performed by the sinc filter. Table XV outlines the bit designations for the Filter register.
PAGE 25
AD7719 Table XVI. IOCON (I/O and Current Source Control Register) Bit Designations Bit Location Bit Name IOCON15 PSW2 Power Switch 2 Control Bit. Set by user to enable power switch P2 to PWRGND. Cleared by user to enable use as a standard I/O pin. When the ADC is in standby mode, the power switches are open. IOCON14 PSW1 Power Switch 1 Control Bit. Set by user to enable power switch P1 to PWRGND. Cleared by user to enable use as a standard I/O pin.
PAGE 26
AD7719 Main ADC Data Result Registers (DATA0): (A3, A2, A1, A0 = 0, 1, 0, 1; Power-On Reset = 0x00 0000) Main ADC Gain Calibration Coefficient Registers (GNO): (A3, A2, A1, A0 = 1, 0, 1, 0; Power-On Reset = 0x5X XXX5) The conversion results for the main ADC channel are stored in the main ADC data register (DATA0). This register is either 16 or 24 bits wide, depending on the status of the WL bit in the main ADC control register (AD0CON). This is a read-only register.
PAGE 27
AD7719 CONFIGURING THE AD7719 MICROCOMPUTER/MICROPROCESSOR INTERFACING All user-accessible registers on the AD7719 are accessed via the serial interface. Communication with any of these registers is initiated by first writing to the Communications register. Figure 11 outlines a flow diagram of the sequence used to configure all registers after a power-up or reset on the AD7719.
PAGE 28
AD7719 START POLL RDY PIN WRITE TO THE COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ FROM THE MODE REGISTER POWER-ON/RESET FOR AD7719 NO CONFIGURE AND INITIALIZE C/ P SERIAL PORT RDY LOW? READ FROM MODE REGISTER YES WRITE TO THE COMMUNICATIONS REGISTER SELECTING NEXT OPERATION TO BE A WRITE TO THE IOCON REGISTER WRITE TO THE COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A WRITE TO THE MODE REGISTER WRITE TO MODE REGISTER SELECTING CONTINUOUS CONVERSION MODE WRITE TO COMM
PAGE 29
AD7719 AD7719-to-68HC11 Interface AD7719-to-8xC51 Interface Figure 12 shows an interface between the AD7719 and the 68HC11 microcontroller. The diagram shows the minimum (3-wire) interface with CS on the AD7719 hardwired low. In this scheme, the RDY bits of the Status register are monitored to determine when the Data register is updated. RDY0 indicates the status of the main ADC channel while RDY1 indicates the status of the aux channel.
PAGE 30
AD7719 AD7719-to-ADSP-2103/ADSP-2105 Interface Figure 14 shows an interface between the AD7719 and the ADSP-2103/ADSP-2105 DSP processor. In the interface shown, the RDY bits of the Status register are again monitored to determine when the Data register is updated. The alternative scheme is to use an interrupt-driven system, in which case the RDY output is connected to the IRQ2 input of the ADSP-2103/ ADSP-2105. The serial interface of the ADSP-2103/ADSP-2105 is set up for alternate framing mode.
PAGE 31
AD7719 Analog Input Channels The main ADC has four associated analog input pins (labeled AIN1 to AIN4) that can be configured as two fully differential input channels or three pseudodifferential input channels. Channel selection bits CH1 and CH0 in the ADC0CON register, along with the CHCON bit of the mode register, detail the different configurations. The auxiliary ADC has four external input pins (labeled AIN3 to AIN6) as well as an internal connection to the internal on-chip temperature sensor.
PAGE 32
AD7719 Table XVIII. Max Resistance for No 16-Bit Gain Error (Unbuffered Mode) External Capacitance Gain 0 pF 50 pF 100 pF 500 pF 1000 pF 5000 pF 1 2 4 8–128 111.3K 53.7K 25.4K 10.7K 27.8K 13.5K 6.4K 2.9K 16.7K 8.1K 3.9K 1.7K 4.5K 2.2K 1.0K 480 2.58K 1.26K 600 270 700 360 170 75 Table XIX. Max Resistance for No 20-Bit Gain Error (Unbuffered Mode) External Capacitance Gain 0 pF 50 pF 100 pF 500 pF 1000 pF 5000 pF 1 2 4 8–128 84.9K 42.0K 20.5K 8.8K 21.1K 10.4K 5.0K 2.3K 12.5K 6.1K 2.
PAGE 33
AD7719 turned off by writing a 0 to the BO bit in the IOCON register. The current sources work over the normal absolute input voltage range specifications with buffers on. Data Output Coding When the ADC is configured for unipolar operation, the output coding is natural (straight) binary with a zero differential input voltage resulting in a code of 000 . . . 000, a midscale voltage resulting in a code of 100 . . . 000, and a full-scale input voltage resulting in a code of 111 . . . 111.
PAGE 34
AD7719 Reference Detect ADC Disable Mode The AD7719 includes on-chip circuitry to detect if the part has a valid reference on the main ADC for conversions or calibrations. If the voltage between the external REFIN1(+) and REFIN1(–) pins goes below 0.3 V or either the REFIN1(+) or REFIN1(–) inputs are open circuit, the AD7719 detects that it no longer has a valid reference. In this case, the NOXREF bit of the Status register is set to 1.
PAGE 35
AD7719 Internally in the AD7719, the coefficients are normalized before being used to scale the words coming out of the digital filter. The offset calibration coefficient is subtracted from the result prior to the multiplication by the gain coefficient. From an operational point of view, a calibration should be treated like another ADC conversion. A zero-scale calibration (if required) should always be carried out before a full-scale calibration.
PAGE 36
AD7719 The circuit in Figure 20 shows a method that utilizes all three pseudodifferential input channels on the AD7719 main channel to temperature-compensate a pressure transducer. Pressure Measurement One typical application of the AD7719 is pressure measurement. Figure 19 shows the AD7719 used with a pressure transducer, the BP01 from Sensym. 5V The pressure transducer is arranged in a bridge network and gives a differential output voltage between its OUT(+) and OUT(–) terminals.
PAGE 37
AD7719 The switched polarity current source is developed using the on-chip current sources and external phase control switches (A and A) driven from the controller. During the conversion process, the AD7719 takes two conversion results, one on each phase. During Phase 1, the on-chip current source is directed to IOUT1 and flows top to bottom through the sensor and switch controlled by A.
PAGE 38
AD7719 In this 3-wire configuration, the lead resistances will result in errors if only one current source is used because the 200 µA will flow through RL1, developing a voltage error between AIN1 and AIN2. In the scheme outlined below, the second RTD current source is used to compensate for the error introduced by the 200 µA flowing through RL1. The second RTD current flows through RL2.
PAGE 39
AD7719 OUTLINE DIMENSIONS 28-Lead Standard Small Outline Package [SOIC] Wide Body (R-28) Dimensions shown in millimeters and (inches) 18.10 (0.7126) 17.70 (0.6969) 28 15 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 10.00 (0.3937) 14 2.65 (0.1043) 2.35 (0.0925) 0.75 (0.0295) ⴛ 45ⴗ 0.25 (0.0098) 0.30 (0.0118) 0.10 (0.0039) 8ⴗ 0ⴗ 1.27 (0.0500) 0.51 (0.0201) SEATING 0.32 (0.0126) PLANE BSC 0.33 (0.0130) 0.23 (0.0091) COPLANARITY 0.10 1.27 (0.0500) 0.40 (0.
PAGE 40
AD7719 Revision History Location Page 4/03—Data Sheet changed from REV. 0 to REV. A. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 –40– REV. A C02460–0–4/03(A) Updated format . . . . . . . . . . . .