Datasheet

REV. A
AD7716
–4–
Limit at T
MIN
, T
MAX
Parameter (B Version) Units Conditions/Comments
f
CLKIN
3, 4
400 kHz min CLKIN Frequency
8 MHz max
t
r
5
40 ns max Digital Output Rise Time. Typically 20 ns
t
f
5
40 ns max Digital Output Fall Time. Typically 20 ns
t
7
1/f
CLKIN
ns min CASCIN Pulse Width
t
8
1/f
CLKIN
ns min CASCIN to DRDY Setup Time
t
9
1/2f
CLKIN
+ 30 ns max DRDY Low to SCLK Low Delay
t
10
50 ns max CLKIN High to DRDY Low, SCLK Active, RFS Active
t
11
40 ns max CLKIN High to SCLK High Delay
t
12
50 ns min SCLK Width
t
13
1/f
CLKIN
ns SCLK Period
t
14
40 ns max SCLK High to RFS High Delay
t
15
1/f
CLKIN
ns RFS Pulse Width
t
16
6
45 ns max SCLK High to SDATA Valid Delay
t
17
7
1/2f
CLKIN
+ 50 ns max SCLK Low to SDATA High Impedance Delay
1/2f
CLKIN
+ 10 ns min
t
18
1/2f
CLKIN
+ 60 ns max CLKIN High to DRDY High Delay
t
19
50 ns max CLKIN High to RFS High Impedance, SCLK High Impedance
20 ns min
t
20
1/2f
CLKIN
+ 50 ns max SCLK Low to CASCOUT High Delay
t
21
2/f
CLKIN
ns CASCOUT Pulse Width
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 1 and 3.
3
CLKIN duty cycle range is 40% to 60%.
4
The AD7716 is production tested with f
CLKIN
at 8 MHz in the slave mode. It is guaranteed by characterization to operate at 400 kHz and 8 MHz in master mode.
5
Specified using 10% and 90% points on waveform of interest.
6
t
16
is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
7
t
17
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
MASTER MODE TIMING CHARACTERISTICS
1, 2
(AV
DD
= DV
DD
= +5 V 6 5%; AV
SS
= –5 V 6 5%; AGND = DGND = 0 V;
f
CLKIN
= 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DV
DD
; unless otherwise noted)
Figure 3. Master Mode Timing Diagram
DB31
CH1
t
20
t
21
CASCIN (I)
SCLK (O)
RFS (O)
SDATA (O)
CASCOUT (O)
t
17
t
8
t
7
t
18
t
19
t
9
t
11
t
10
t
12
t
13
t
12
t
19
t
15
t
14
t
16
DB30
CH1
DB29
CH1
DB25
CH1
DB24
CH1
DB23
CH1
DB2
CH4
DB1
CH4
DB0
CH4
CLKIN (I)
DRDY (O)