Datasheet

REV. A
–3–
AD7716
Table I. Typical Usable Dynamic Range, RMS Noise and Filter Settling Time vs. Filter Cutoff Frequency
Programmed Cutoff Output Update Usable Dynamic RMS Noise Filter Settling Time to Absolute Group
N Frequency (Hz) Rate (Hz) Range (dB) (mV) 60.0007% FS (ms) Delay (ms)
0 584 2232 99 21 1.35 0.675
1 292 1116 102 14 2.7 1.35
2 146 558 105 10 5.4 2.7
3 73 279 108 7 10.8 5.4
4 36.5 140 111 5 21.6 10.8
NOTE
Usable Dynamic Range is defined as the ratio of the rms full-scale reading (sine wave input) to the rms noise of the converter.
CONTROL REGISTER TIMING CHARACTERISTICS
1, 2
(AV
DD
= DV
DD
= +5 V 6 5%; AV
SS
= –5 V 6 5%; AGND =
DGND = 0 V; f
CLKIN
= 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DV
DD
; unless otherwise noted)
Limit at T
MIN
, T
MAX
Parameter (B Version) Units Conditions/Comments
t
1
1/f
CLKIN
ns min SCLK Period
t
2
77 ns min SCLK Width
t
3
30 ns min TFS Setup Time
t
4
20 ns min SDATA Setup Time
t
5
10 ns min SDATA Hold Time
t
6
20 ns min TFS Hold Time
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figure 2.
3
CLKIN Duty Cycle range is 40% to 60%.
200µA
I
OH
+2.1V
TO
OUTPUT
PIN
1.6mA
C
L
50pF
I
OL
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
DB4
(DB12)
DB3
(DB11)
DB2
(DB10)
DB1
(DB9)
DB0
(DB8)
DB5
(DB13)
DB6
(DB14)
DB7
(DB15)
t
2
SCLK (I)
SDATA (I)
TFS (I)
t
2
t
5
t
4
t
3
t
6
t
1
Figure 2. Control Register Timing Diagram