Datasheet

AD7715
Rev. D | Page 8 of 40
TIMING CHARACTERISTICS
DV
DD
= 3 V to 5.25 V; AV
DD
= 3 V to 5.25 V; AGND = DGND = 0 V; f
CLKIN
= 2.4576 MHz; Input Logic 0 = 0 V, Logic 1 = DV
DD
, unless
otherwise noted.
Table 4.
Parameter
1, 2
Limit at T
MIN
, T
MAX
(A Version)
Unit Conditions/Comments
f
CLKIN
3, 4
400 kHz min
2.5 MHz max
Master clock frequency: crystal oscillator or externally supplied for specified
performance
t
CLK IN LO
0.4 × t
CLK IN
ns min Master clock input low time; t
CLK IN
= 1/f
CLK IN
t
CLK IN HI
0.4 × t
CLK IN
ns min Master clock input high time
t
1
500 × t
CLK IN
ns nom
DRDY
high time
t
2
100 ns min
RESET
pulsewidth
Read Operation
t
3
0 ns min
DRDY
to CS setup time
t
4
120 ns min
CS
falling edge to SCLK rising edge setup time
t
5
5
0 ns min SCLK falling edge to data valid delay
80 ns max DV
DD
= 5 V
100 ns max DV
DD
= 3.3 V
t
6
100 ns min SCLK high pulsewidth
t
7
100 ns min SCLK low pulsewidth
t
8
0 ns min
CS
rising edge to SCLK rising edge hold time
t
9
6
10 ns min Bus relinquish time after SCLK rising edge
60 ns max DV
DD
= +5 V
100 ns max DV
DD
= +3.3 V
t
10
100 ns max
SCLK falling edge to DRDY
high
7
Write Operation
t
11
120 ns min
CS
falling edge to SCLK rising edge setup time
t
12
30 ns min Data valid to SCLK rising edge setup time
t
13
20 ns min Data valid to SCLK rising edge hold time
t
14
100 ns min SCLK high pulsewidth
t
15
100 ns min SCLK low pulsewidth
t
16
0 ns min
CS
rising edge to SCLK rising edge hold time
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 8 and Figure 9.
3
CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7715 is not in standby mode. If no clock is present in this case, the device can draw
higher current than specified and possibly become uncalibrated.
4
The AD7715 is production tested with f
CLKIN
at 2.4576 MHz (1 MHz for some I
DD
tests). It is guaranteed by characterization to operate at 400 kHz.
5
These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
7
DRDY
returns high after the first read from the device after an output update. The same data can be read again, if required, while
DRDY
is high although take care that
subsequent reads do not occur close to the next output update.
TO
OUTPUT
PIN
+1.6V
I
SINK
(800µA AT DV
DD
= 5V
100µA AT DV
DD
= 3.3V)
I
SOURCE
(200µA AT DV
DD
= 5V
100µA AT DV
DD
= 3.3V)
50pF
08519-002
Figure 2. Load Circuit for Access Time and Bus Relinquish Time